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54 lines
2.4 KiB
LLVM
54 lines
2.4 KiB
LLVM
; RUN: llc -march=hexagon -mhvx < %s | FileCheck %s
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; Check that Hexagon Vector Combine do not create vmem for adjacent
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; loads less than 4.
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; Test 1: We have three adjacent loads. By default, we won't produce vmem
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; for loads less than 4.
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; CHECK-LABEL: @foo1
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; CHECK: vmemu(
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; CHECK-NOT: vmem(
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define <32 x i32> @foo1(ptr %iptr) #0 align 32 {
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entry:
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%0 = load <32 x i32>, ptr %iptr, align 1
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%add.ptr = getelementptr inbounds i8, ptr %iptr, i32 128
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%1 = load <32 x i32>, ptr %add.ptr, align 1
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%add.ptr2 = getelementptr inbounds i8, ptr %iptr, i32 256
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%2 = load <32 x i32>, ptr %add.ptr2, align 1
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%3 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %1, <32 x i32> %0)
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%4 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %3)
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%5 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %2, <32 x i32> %1)
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%6 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %5)
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%7 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %4, <32 x i32> %6)
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%8 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %7)
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ret <32 x i32> %8
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}
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; Test 2: We have four adjacent loads. Thus, we will produce vmem.
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; CHECK-LABEL: @foo2
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; CHECK: vmem(
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; CHECK-NOT: vmemu
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define <32 x i32> @foo2(ptr %iptr) #0 align 32 {
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entry:
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%0 = load <32 x i32>, ptr %iptr, align 1
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%add.ptr = getelementptr inbounds i8, ptr %iptr, i32 128
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%1 = load <32 x i32>, ptr %add.ptr, align 1
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%add.ptr2 = getelementptr inbounds i8, ptr %iptr, i32 256
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%2 = load <32 x i32>, ptr %add.ptr2, align 1
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%add.ptr4 = getelementptr inbounds i8, ptr %iptr, i32 512
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%3 = load <32 x i32>, ptr %add.ptr4, align 1
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%4 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %1, <32 x i32> %0)
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%5 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %4)
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%6 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %3, <32 x i32> %2)
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%7 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %6)
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%8 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %5, <32 x i32> %7)
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%9 = tail call <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32> %8)
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ret <32 x i32> %9
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}
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declare <32 x i32> @llvm.hexagon.V6.vconv.hf.qf32.128B(<64 x i32>) #1
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declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
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attributes #0 = {"target-features"="+hvx-length128b,+hvxv75" }
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