derek.holloway
7502bf64a4
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36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=hexagon -enable-pipeliner -verify-machineinstrs < %s
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; REQUIRES: asserts
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; This test fails in the machine verifier because the verifier thinks the
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; return register is undefined, and because there is a basic block that
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; ends with an unconditional branch that is not marked as a barrier.
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;
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; Enabling SWP exposes these bugs because the live variable analysis is
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; performed earlier than the process implicit def pass. This ordering
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; causes the JMPR machine instruction to contain two R0 operands, one
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; with an undef and one with a kill flag.
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@g0 = common global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @f0(i32 %a0) #0 {
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b0:
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%v0 = icmp eq i32 %a0, 0
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br i1 %v0, label %b2, label %b1
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b1: ; preds = %b0
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%v1 = tail call i32 @f1(i32 %a0) #0
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br label %b3
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b2: ; preds = %b0
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store i32 0, ptr @g0, align 4
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br label %b3
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b3: ; preds = %b2, %b1
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ret i32 undef
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}
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declare i32 @f1(...)
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attributes #0 = { nounwind }
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