derek.holloway
7502bf64a4
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92 lines
3.8 KiB
LLVM
92 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+f,+d < %s | FileCheck %s --check-prefix=LA64
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; Check the GHC call convention works (la64)
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@base = external dso_local global i64 ; assigned to register: s0
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@sp = external dso_local global i64 ; assigned to register: s1
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@hp = external dso_local global i64 ; assigned to register: s2
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@r1 = external dso_local global i64 ; assigned to register: s3
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@r2 = external dso_local global i64 ; assigned to register: s4
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@r3 = external dso_local global i64 ; assigned to register: s5
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@r4 = external dso_local global i64 ; assigned to register: s6
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@r5 = external dso_local global i64 ; assigned to register: s7
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@splim = external dso_local global i64 ; assigned to register: s8
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@f1 = external dso_local global float ; assigned to register: fs0
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@f2 = external dso_local global float ; assigned to register: fs1
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@f3 = external dso_local global float ; assigned to register: fs2
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@f4 = external dso_local global float ; assigned to register: fs3
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@d1 = external dso_local global double ; assigned to register: fs4
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@d2 = external dso_local global double ; assigned to register: fs5
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@d3 = external dso_local global double ; assigned to register: fs6
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@d4 = external dso_local global double ; assigned to register: fs7
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define ghccc void @foo() nounwind {
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; LA64-LABEL: foo:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(d4)
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; LA64-NEXT: fld.d $fs7, $a0, %pc_lo12(d4)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(d3)
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; LA64-NEXT: fld.d $fs6, $a0, %pc_lo12(d3)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(d2)
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; LA64-NEXT: fld.d $fs5, $a0, %pc_lo12(d2)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(d1)
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; LA64-NEXT: fld.d $fs4, $a0, %pc_lo12(d1)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(f4)
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; LA64-NEXT: fld.s $fs3, $a0, %pc_lo12(f4)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(f3)
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; LA64-NEXT: fld.s $fs2, $a0, %pc_lo12(f3)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(f2)
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; LA64-NEXT: fld.s $fs1, $a0, %pc_lo12(f2)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(f1)
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; LA64-NEXT: fld.s $fs0, $a0, %pc_lo12(f1)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(splim)
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; LA64-NEXT: ld.d $s8, $a0, %pc_lo12(splim)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(r5)
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; LA64-NEXT: ld.d $s7, $a0, %pc_lo12(r5)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(r4)
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; LA64-NEXT: ld.d $s6, $a0, %pc_lo12(r4)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(r3)
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; LA64-NEXT: ld.d $s5, $a0, %pc_lo12(r3)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(r2)
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; LA64-NEXT: ld.d $s4, $a0, %pc_lo12(r2)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(r1)
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; LA64-NEXT: ld.d $s3, $a0, %pc_lo12(r1)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(hp)
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; LA64-NEXT: ld.d $s2, $a0, %pc_lo12(hp)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(sp)
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; LA64-NEXT: ld.d $s1, $a0, %pc_lo12(sp)
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; LA64-NEXT: pcalau12i $a0, %pc_hi20(base)
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; LA64-NEXT: ld.d $s0, $a0, %pc_lo12(base)
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; LA64-NEXT: pcaddu18i $t8, %call36(bar)
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; LA64-NEXT: jr $t8
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entry:
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%0 = load double, ptr @d4
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%1 = load double, ptr @d3
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%2 = load double, ptr @d2
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%3 = load double, ptr @d1
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%4 = load float, ptr @f4
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%5 = load float, ptr @f3
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%6 = load float, ptr @f2
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%7 = load float, ptr @f1
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%8 = load i64, ptr @splim
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%9 = load i64, ptr @r5
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%10 = load i64, ptr @r4
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%11 = load i64, ptr @r3
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%12 = load i64, ptr @r2
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%13 = load i64, ptr @r1
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%14 = load i64, ptr @hp
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%15 = load i64, ptr @sp
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%16 = load i64, ptr @base
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tail call ghccc void @bar(i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
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i64 %11, i64 %10, i64 %9, i64 %8, float %7, float %6,
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float %5, float %4, double %3, double %2, double %1, double %0) nounwind
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ret void
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}
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declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64,
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float, float, float, float,
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double, double, double, double)
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