derek.holloway
7502bf64a4
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69 lines
2.0 KiB
LLVM
69 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define <16 x i8> @bitsel_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind {
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; CHECK-LABEL: bitsel_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vbitsel.v $vr0, $vr0, $vr1, $vr2
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; CHECK-NEXT: ret
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entry:
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%0 = and <16 x i8> %c, %b
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%1 = xor <16 x i8> %c, splat (i8 -1)
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%2 = and <16 x i8> %a, %1
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%3 = or <16 x i8> %0, %2
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ret <16 x i8> %3
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}
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define <8 x i16> @bitsel_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind {
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; CHECK-LABEL: bitsel_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vbitsel.v $vr0, $vr0, $vr1, $vr2
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; CHECK-NEXT: ret
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entry:
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%0 = and <8 x i16> %c, %b
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%1 = xor <8 x i16> %c, splat (i16 -1)
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%2 = and <8 x i16> %a, %1
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%3 = or <8 x i16> %0, %2
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ret <8 x i16> %3
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}
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define <4 x i32> @bitsel_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind {
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; CHECK-LABEL: bitsel_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vbitsel.v $vr0, $vr0, $vr1, $vr2
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; CHECK-NEXT: ret
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entry:
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%0 = and <4 x i32> %c, %b
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%1 = xor <4 x i32> %c, splat (i32 -1)
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%2 = and <4 x i32> %a, %1
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%3 = or <4 x i32> %0, %2
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ret <4 x i32> %3
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}
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define <2 x i64> @bitsel_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind {
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; CHECK-LABEL: bitsel_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vbitsel.v $vr0, $vr0, $vr1, $vr2
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; CHECK-NEXT: ret
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entry:
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%0 = and <2 x i64> %c, %b
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%1 = xor <2 x i64> %c, splat (i64 -1)
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%2 = and <2 x i64> %a, %1
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%3 = or <2 x i64> %0, %2
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ret <2 x i64> %3
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}
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define <16 x i8> @bitsel_v16i8_1(<16 x i8> %a, <16 x i8> %b) nounwind {
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; CHECK-LABEL: bitsel_v16i8_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vbitseli.b $vr0, $vr1, 1
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; CHECK-NEXT: ret
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entry:
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%0 = and <16 x i8> %a, splat (i8 1)
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%1 = xor <16 x i8> %a, splat (i8 -1)
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%2 = and <16 x i8> %b, %1
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%3 = or <16 x i8> %0, %2
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ret <16 x i8> %3
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}
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