derek.holloway
7502bf64a4
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50 lines
1.4 KiB
LLVM
50 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
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; RUN: --check-prefixes=ASM,ALL
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; RUN: llc -mtriple=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
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; RUN: llvm-objdump --no-print-imm-hex -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL
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; Test that spill and reloads use the dsp "variant" instructions. We use -O0
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; to use the simple register allocator.
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; To test the micromips output, we have to take a round trip through the
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; object file encoder/decoder as the instruction mapping tables are used to
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; support micromips.
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; FIXME: We should be able to get rid of those instructions with the variable
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; value registers.
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; ALL-LABEL: spill_reload{{>?}}:
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define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {
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entry:
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%c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b)
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%cond = icmp eq i32 %g, 0
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br i1 %cond, label %true, label %end
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; ASM: SWDSP
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; ASM: SWDSP
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; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
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; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
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true:
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ret <4 x i8> %c
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; ASM: LWDSP
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; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
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end:
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%d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a)
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ret <4 x i8> %d
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; ASM: LWDSP
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; ASM: LWDSP
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; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
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; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
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}
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declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
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