derek.holloway
7502bf64a4
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134 lines
4.2 KiB
LLVM
134 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2
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; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS32
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS64
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; RUN: llc < %s -mtriple=mips -mcpu=mips2 -O0 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2-O0
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; RUN: llc < %s -mtriple=mips -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS32-O0
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define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b, i32 signext %c) {
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; MIPS2-LABEL: sdiv_i32:
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; MIPS2: # %bb.0: # %entry
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; MIPS2-NEXT: div $zero, $4, $5
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; MIPS2-NEXT: teq $5, $zero, 7
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; MIPS2-NEXT: mflo $1
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; MIPS2-NEXT: nop
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; MIPS2-NEXT: nop
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; MIPS2-NEXT: div $zero, $1, $6
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; MIPS2-NEXT: teq $6, $zero, 7
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; MIPS2-NEXT: mflo $2
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; MIPS2-NEXT: jr $ra
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; MIPS2-NEXT: nop
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;
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; MIPS32-LABEL: sdiv_i32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: div $zero, $4, $5
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; MIPS32-NEXT: teq $5, $zero, 7
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; MIPS32-NEXT: mflo $1
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; MIPS32-NEXT: div $zero, $1, $6
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; MIPS32-NEXT: teq $6, $zero, 7
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mflo $2
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;
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entry:
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%sdiv = sdiv i32 %a, %b
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%sdiv1 = sdiv i32 %sdiv, %c
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ret i32 %sdiv1
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}
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define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b, i64 signext %c) {
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; MIPS3-LABEL: sdiv_i64:
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; MIPS3: # %bb.0: # %entry
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; MIPS3-NEXT: ddiv $zero, $4, $5
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; MIPS3-NEXT: teq $5, $zero, 7
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; MIPS3-NEXT: mflo $1
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; MIPS3-NEXT: nop
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; MIPS3-NEXT: nop
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; MIPS3-NEXT: ddiv $zero, $1, $6
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; MIPS3-NEXT: teq $6, $zero, 7
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; MIPS3-NEXT: mflo $2
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; MIPS3-NEXT: jr $ra
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; MIPS3-NEXT: nop
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;
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; MIPS64-LABEL: sdiv_i64:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: ddiv $zero, $4, $5
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; MIPS64-NEXT: teq $5, $zero, 7
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; MIPS64-NEXT: mflo $1
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; MIPS64-NEXT: ddiv $zero, $1, $6
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; MIPS64-NEXT: teq $6, $zero, 7
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mflo $2
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;
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entry:
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%sdiv = sdiv i64 %a, %b
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%sdiv1 = sdiv i64 %sdiv, %c
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ret i64 %sdiv1
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}
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define signext i32 @sdiv_lw_sdiv_i32(i32 signext %a, i32 signext %b, i32 signext %c) {
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; MIPS2-O0-LABEL: sdiv_lw_sdiv_i32:
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; MIPS2-O0: # %bb.0: # %entry
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; MIPS2-O0-NEXT: addiu $sp, $sp, -16
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; MIPS2-O0-NEXT: .cfi_def_cfa_offset 16
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; MIPS2-O0-NEXT: sw $4, 12($sp)
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; MIPS2-O0-NEXT: sw $5, 8($sp)
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; MIPS2-O0-NEXT: sw $6, 4($sp)
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; MIPS2-O0-NEXT: lw $2, 12($sp)
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; MIPS2-O0-NEXT: lw $1, 8($sp)
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; MIPS2-O0-NEXT: div $zero, $2, $1
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; MIPS2-O0-NEXT: teq $1, $zero, 7
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; MIPS2-O0-NEXT: mflo $2
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; MIPS2-O0-NEXT: lw $1, 4($sp)
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; MIPS2-O0-NEXT: nop
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; MIPS2-O0-NEXT: div $zero, $2, $1
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; MIPS2-O0-NEXT: teq $1, $zero, 7
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; MIPS2-O0-NEXT: mflo $2
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; MIPS2-O0-NEXT: addiu $sp, $sp, 16
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; MIPS2-O0-NEXT: jr $ra
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; MIPS2-O0-NEXT: nop
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;
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; MIPS32-O0-LABEL: sdiv_lw_sdiv_i32:
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; MIPS32-O0: # %bb.0: # %entry
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; MIPS32-O0-NEXT: addiu $sp, $sp, -16
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; MIPS32-O0-NEXT: .cfi_def_cfa_offset 16
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; MIPS32-O0-NEXT: sw $4, 12($sp)
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; MIPS32-O0-NEXT: sw $5, 8($sp)
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; MIPS32-O0-NEXT: sw $6, 4($sp)
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; MIPS32-O0-NEXT: lw $2, 12($sp)
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; MIPS32-O0-NEXT: lw $1, 8($sp)
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; MIPS32-O0-NEXT: div $zero, $2, $1
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; MIPS32-O0-NEXT: teq $1, $zero, 7
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; MIPS32-O0-NEXT: mflo $2
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; MIPS32-O0-NEXT: lw $1, 4($sp)
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; MIPS32-O0-NEXT: div $zero, $2, $1
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; MIPS32-O0-NEXT: teq $1, $zero, 7
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; MIPS32-O0-NEXT: mflo $2
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; MIPS32-O0-NEXT: addiu $sp, $sp, 16
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; MIPS32-O0-NEXT: jr $ra
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; MIPS32-O0-NEXT: nop
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;
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%c.addr = alloca i32, align 4
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store i32 %a, ptr %a.addr, align 4
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store i32 %b, ptr %b.addr, align 4
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store i32 %c, ptr %c.addr, align 4
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%0 = load i32, ptr %a.addr, align 4
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%1 = load i32, ptr %b.addr, align 4
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%sdiv = sdiv i32 %0, %1
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%2 = load i32, ptr %c.addr, align 4
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%sdiv1 = sdiv i32 %sdiv, %2
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ret i32 %sdiv1
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}
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