derek.holloway
7502bf64a4
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208 lines
8.4 KiB
LLVM
208 lines
8.4 KiB
LLVM
; Test the MSA intrinsics that are encoded with the ELM instruction format and
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; are element extraction operations.
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; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
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; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
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; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
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; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
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@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_copy_s_b_RES = global i32 0, align 16
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define void @llvm_mips_copy_s_b_test() nounwind {
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entry:
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%0 = load <16 x i8>, ptr @llvm_mips_copy_s_b_ARG1
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%1 = tail call i32 @llvm.mips.copy.s.b(<16 x i8> %0, i32 1)
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store i32 %1, ptr @llvm_mips_copy_s_b_RES
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ret void
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}
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declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_s_b_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_b_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_ARG1)
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; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS-ANY-DAG: copy_s.b [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES)
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; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_s_b_test
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;
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@llvm_mips_copy_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_copy_s_h_RES = global i32 0, align 16
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define void @llvm_mips_copy_s_h_test() nounwind {
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entry:
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%0 = load <8 x i16>, ptr @llvm_mips_copy_s_h_ARG1
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%1 = tail call i32 @llvm.mips.copy.s.h(<8 x i16> %0, i32 1)
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store i32 %1, ptr @llvm_mips_copy_s_h_RES
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ret void
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}
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declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_s_h_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_h_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_ARG1)
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; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS-ANY-DAG: copy_s.h [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES)
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; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_s_h_test
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;
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@llvm_mips_copy_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_copy_s_w_RES = global i32 0, align 16
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define void @llvm_mips_copy_s_w_test() nounwind {
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entry:
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%0 = load <4 x i32>, ptr @llvm_mips_copy_s_w_ARG1
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%1 = tail call i32 @llvm.mips.copy.s.w(<4 x i32> %0, i32 1)
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store i32 %1, ptr @llvm_mips_copy_s_w_RES
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ret void
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}
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declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_s_w_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_w_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_ARG1)
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; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS-ANY-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES)
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; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_s_w_test
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;
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@llvm_mips_copy_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_copy_s_d_RES = global i64 0, align 16
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define void @llvm_mips_copy_s_d_test() nounwind {
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entry:
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%0 = load <2 x i64>, ptr @llvm_mips_copy_s_d_ARG1
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%1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1)
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store i64 %1, ptr @llvm_mips_copy_s_d_RES
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ret void
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}
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declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_s_d_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_d_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_ARG1)
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; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
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; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
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; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_d_RES)
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; MIPS32-DAG: sw [[RD1]], 0([[RES]])
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; MIPS32-DAG: sw [[RD2]], 4([[RES]])
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; MIPS64-DAG: sd [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_s_d_test
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;
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@llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_copy_u_b_RES = global i32 0, align 16
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define void @llvm_mips_copy_u_b_test() nounwind {
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entry:
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%0 = load <16 x i8>, ptr @llvm_mips_copy_u_b_ARG1
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%1 = tail call i32 @llvm.mips.copy.u.b(<16 x i8> %0, i32 1)
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store i32 %1, ptr @llvm_mips_copy_u_b_RES
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ret void
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}
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declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_u_b_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_b_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_ARG1)
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; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS-ANY-DAG: copy_u.b [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_b_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_b_RES)
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; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_u_b_test
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;
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@llvm_mips_copy_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_copy_u_h_RES = global i32 0, align 16
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define void @llvm_mips_copy_u_h_test() nounwind {
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entry:
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%0 = load <8 x i16>, ptr @llvm_mips_copy_u_h_ARG1
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%1 = tail call i32 @llvm.mips.copy.u.h(<8 x i16> %0, i32 1)
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store i32 %1, ptr @llvm_mips_copy_u_h_RES
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ret void
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}
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declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_u_h_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_h_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_ARG1)
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; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS-ANY-DAG: copy_u.h [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_h_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_h_RES)
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; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_u_h_test
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;
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@llvm_mips_copy_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_copy_u_w_RES = global i32 0, align 16
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define void @llvm_mips_copy_u_w_test() nounwind {
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entry:
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%0 = load <4 x i32>, ptr @llvm_mips_copy_u_w_ARG1
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%1 = tail call i32 @llvm.mips.copy.u.w(<4 x i32> %0, i32 1)
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store i32 %1, ptr @llvm_mips_copy_u_w_RES
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ret void
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}
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declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_u_w_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1)
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; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS32-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS64-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES)
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; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_u_w_test
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;
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@llvm_mips_copy_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_copy_u_d_RES = global i64 0, align 16
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define void @llvm_mips_copy_u_d_test() nounwind {
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entry:
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%0 = load <2 x i64>, ptr @llvm_mips_copy_u_d_ARG1
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%1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1)
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store i64 %1, ptr @llvm_mips_copy_u_d_RES
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ret void
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}
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declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind
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; MIPS-ANY: llvm_mips_copy_u_d_test:
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; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_d_ARG1)
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; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_ARG1)
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; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
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; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
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; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1]
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; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES)
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; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES)
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; MIPS32-DAG: sw [[RD1]], 0([[RES]])
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; MIPS32-DAG: sw [[RD2]], 4([[RES]])
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; MIPS64-DAG: sd [[RD]], 0([[RES]])
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; MIPS-ANY: .size llvm_mips_copy_u_d_test
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;
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