derek.holloway
7502bf64a4
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70 lines
2.6 KiB
LLVM
70 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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;; Test the strict-align feature which is similar to AArch64/arm64-strict-align.ll.
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; RUN: llc --mtriple=mipsisa32r6 < %s | FileCheck %s --check-prefix=MIPS32R6-UNALIGNED
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; RUN: llc --mtriple=mipsisa32r6 --mattr=-strict-align < %s | FileCheck %s --check-prefix=MIPS32R6-UNALIGNED
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; RUN: llc --mtriple=mipsisa32r6 --mattr=+strict-align < %s | FileCheck %s --check-prefix=MIPS32R6-ALIGNED
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; RUN: llc --mtriple=mipsisa64r6 < %s | FileCheck %s --check-prefix=MIPS64R6-UNALIGNED
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; RUN: llc --mtriple=mipsisa64r6 --mattr=-strict-align < %s | FileCheck %s --check-prefix=MIPS64R6-UNALIGNED
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; RUN: llc --mtriple=mipsisa64r6 --mattr=+strict-align < %s | FileCheck %s --check-prefix=MIPS64R6-ALIGNED
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define i32 @f0(ptr %p) nounwind {
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; MIPS32R6-UNALIGNED-LABEL: f0:
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; MIPS32R6-UNALIGNED: # %bb.0:
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; MIPS32R6-UNALIGNED-NEXT: lw $2, 0($4)
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; MIPS32R6-UNALIGNED-NEXT: jrc $ra
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;
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; MIPS32R6-ALIGNED-LABEL: f0:
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; MIPS32R6-ALIGNED: # %bb.0:
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; MIPS32R6-ALIGNED-NEXT: lhu $1, 2($4)
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; MIPS32R6-ALIGNED-NEXT: lhu $2, 0($4)
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; MIPS32R6-ALIGNED-NEXT: sll $2, $2, 16
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; MIPS32R6-ALIGNED-NEXT: jr $ra
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; MIPS32R6-ALIGNED-NEXT: or $2, $2, $1
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;
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; MIPS64R6-UNALIGNED-LABEL: f0:
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; MIPS64R6-UNALIGNED: # %bb.0:
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; MIPS64R6-UNALIGNED-NEXT: lw $2, 0($4)
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; MIPS64R6-UNALIGNED-NEXT: jrc $ra
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;
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; MIPS64R6-ALIGNED-LABEL: f0:
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; MIPS64R6-ALIGNED: # %bb.0:
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; MIPS64R6-ALIGNED-NEXT: lhu $1, 2($4)
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; MIPS64R6-ALIGNED-NEXT: lhu $2, 0($4)
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; MIPS64R6-ALIGNED-NEXT: sll $2, $2, 16
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; MIPS64R6-ALIGNED-NEXT: jr $ra
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; MIPS64R6-ALIGNED-NEXT: or $2, $2, $1
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%tmp = load i32, ptr %p, align 2
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ret i32 %tmp
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}
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define i64 @f1(ptr %p) nounwind {
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; MIPS32R6-UNALIGNED-LABEL: f1:
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; MIPS32R6-UNALIGNED: # %bb.0:
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; MIPS32R6-UNALIGNED-NEXT: lw $2, 0($4)
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; MIPS32R6-UNALIGNED-NEXT: lw $3, 4($4)
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; MIPS32R6-UNALIGNED-NEXT: jrc $ra
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;
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; MIPS32R6-ALIGNED-LABEL: f1:
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; MIPS32R6-ALIGNED: # %bb.0:
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; MIPS32R6-ALIGNED-NEXT: lw $2, 0($4)
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; MIPS32R6-ALIGNED-NEXT: lw $3, 4($4)
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; MIPS32R6-ALIGNED-NEXT: jrc $ra
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;
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; MIPS64R6-UNALIGNED-LABEL: f1:
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; MIPS64R6-UNALIGNED: # %bb.0:
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; MIPS64R6-UNALIGNED-NEXT: ld $2, 0($4)
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; MIPS64R6-UNALIGNED-NEXT: jrc $ra
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;
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; MIPS64R6-ALIGNED-LABEL: f1:
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; MIPS64R6-ALIGNED: # %bb.0:
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; MIPS64R6-ALIGNED-NEXT: lwu $1, 4($4)
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; MIPS64R6-ALIGNED-NEXT: lwu $2, 0($4)
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; MIPS64R6-ALIGNED-NEXT: dsll $2, $2, 32
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; MIPS64R6-ALIGNED-NEXT: jr $ra
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; MIPS64R6-ALIGNED-NEXT: or $2, $2, $1
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%tmp = load i64, ptr %p, align 4
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ret i64 %tmp
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}
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