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80 lines
2.0 KiB
LLVM
80 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=mips64el -mcpu=r5900 < %s | FileCheck %s
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;
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; R5900 FPU does not implement IEEE 754 NaN or infinity. Arithmetic operations
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; use software libcall fallbacks by default for IEEE correctness. Hardware FPU
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; instructions are used when per-instruction nnan+ninf flags guarantee no NaN
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; or infinity inputs/outputs.
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define float @test_fadd(float %a, float %b) {
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; CHECK-LABEL: test_fadd:
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; CHECK: jal __addsf3
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%result = fadd float %a, %b
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ret float %result
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}
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define float @test_fsub(float %a, float %b) {
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; CHECK-LABEL: test_fsub:
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; CHECK: jal __subsf3
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%result = fsub float %a, %b
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ret float %result
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}
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define float @test_fmul(float %a, float %b) {
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; CHECK-LABEL: test_fmul:
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; CHECK: jal __mulsf3
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%result = fmul float %a, %b
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ret float %result
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}
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define float @test_fdiv(float %a, float %b) {
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; CHECK-LABEL: test_fdiv:
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; CHECK: jal __divsf3
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%result = fdiv float %a, %b
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ret float %result
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}
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define float @test_fsqrt(float %a) {
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; CHECK-LABEL: test_fsqrt:
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; CHECK: jal sqrtf
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%result = call float @llvm.sqrt.f32(float %a)
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ret float %result
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}
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; Per-instruction nnan+ninf flags select hardware directly.
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define float @test_fadd_nnan_ninf(float %a, float %b) {
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; CHECK-LABEL: test_fadd_nnan_ninf:
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; CHECK: add.s
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%result = fadd nnan ninf float %a, %b
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ret float %result
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}
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define float @test_fsub_nnan_ninf(float %a, float %b) {
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; CHECK-LABEL: test_fsub_nnan_ninf:
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; CHECK: sub.s
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%result = fsub nnan ninf float %a, %b
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ret float %result
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}
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define float @test_fmul_nnan_ninf(float %a, float %b) {
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; CHECK-LABEL: test_fmul_nnan_ninf:
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; CHECK: mul.s
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%result = fmul nnan ninf float %a, %b
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ret float %result
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}
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define float @test_fdiv_nnan_ninf(float %a, float %b) {
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; CHECK-LABEL: test_fdiv_nnan_ninf:
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; CHECK: div.s
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%result = fdiv nnan ninf float %a, %b
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ret float %result
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}
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define float @test_fsqrt_nnan_ninf(float %a) {
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; CHECK-LABEL: test_fsqrt_nnan_ninf:
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; CHECK: sqrt.s
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%result = call nnan ninf float @llvm.sqrt.f32(float %a)
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ret float %result
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}
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declare float @llvm.sqrt.f32(float)
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