derek.holloway
7502bf64a4
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54 lines
1.7 KiB
LLVM
54 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mcpu=sm_100 < %s | FileCheck %s
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; RUN: %if ptxas-sm_100 %{ llc < %s -mcpu=sm_100 | %ptxas-verify -arch=sm_100 %}
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; NOTE: Currently SETP inversions require all users to be CBranch. However other users like selects
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; can also be processed.
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target triple = "nvptx64-nvidia-cuda"
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define i32 @test_multiple_users(i32 %a, i32 %b) {
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; CHECK-LABEL: test_multiple_users(
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; CHECK: {
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; CHECK-NEXT: .reg .pred %p<3>;
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; CHECK-NEXT: .reg .b32 %r<6>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: ld.param.b32 %r3, [test_multiple_users_param_1];
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; CHECK-NEXT: ld.param.b32 %r2, [test_multiple_users_param_0];
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; CHECK-NEXT: setp.eq.b32 %p1, %r2, %r3;
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; CHECK-NEXT: mov.b32 %r5, 0;
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; CHECK-NEXT: @%p1 bra $L__BB0_2;
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; CHECK-NEXT: // %bb.1: // %then
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; CHECK-NEXT: mov.b32 %r5, 1;
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; CHECK-NEXT: $L__BB0_2: // %merge1
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; CHECK-NEXT: setp.ne.b32 %p2, %r2, %r3;
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; CHECK-NEXT: selp.b32 %r1, 1, 0, %p2;
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; CHECK-NEXT: @%p2 bra $L__BB0_4;
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; CHECK-NEXT: // %bb.3: // %else
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; CHECK-NEXT: mov.b32 %r5, 0;
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; CHECK-NEXT: $L__BB0_4: // %merge2
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; CHECK-NEXT: add.s32 %r4, %r5, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
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; CHECK-NEXT: ret;
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entry:
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%cmp1 = icmp eq i32 %a, %b
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br i1 %cmp1, label %merge1, label %then
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then:
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br label %merge1
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merge1:
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%phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
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%cmp2 = icmp ne i32 %a, %b
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%val = select i1 %cmp2, i32 1, i32 0
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br i1 %cmp2, label %merge2, label %else
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else:
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br label %merge2
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merge2:
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%phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
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%ret = add i32 %phi2, %val
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ret i32 %ret
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}
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