derek.holloway
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83 lines
3.1 KiB
LLVM
83 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt < %s -S -nvptx-mark-kernel-ptrs-global | FileCheck %s --check-prefix IR
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; RUN: llc < %s -mcpu=sm_20 --mtriple nvptx64-nvidia-cuda | FileCheck %s --check-prefixes PTXC
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; RUN: llc < %s -mcpu=sm_20 --mtriple nvptx64-nvidia-nvcl | FileCheck %s --check-prefixes PTXO
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; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 | %ptxas-verify %}
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target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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define ptx_kernel void @ptr_as_int(i64 noundef %i, i32 noundef %v) {
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; IR-LABEL: define ptx_kernel void @ptr_as_int(
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; IR-SAME: i64 noundef [[I:%.*]], i32 noundef [[V:%.*]]) {
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; IR-NEXT: [[P:%.*]] = inttoptr i64 [[I]] to ptr
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; IR-NEXT: [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1)
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; IR-NEXT: [[P2:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr
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; IR-NEXT: store i32 [[V]], ptr [[P2]], align 4
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; IR-NEXT: ret void
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;
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; PTXC-LABEL: ptr_as_int(
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; PTXC: {
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; PTXC-NEXT: .reg .b32 %r<2>;
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; PTXC-NEXT: .reg .b64 %rd<3>;
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; PTXC-EMPTY:
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; PTXC-NEXT: // %bb.0:
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; PTXC-NEXT: ld.param.b64 %rd1, [ptr_as_int_param_0];
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; PTXC-NEXT: ld.param.b32 %r1, [ptr_as_int_param_1];
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; PTXC-NEXT: cvta.to.global.u64 %rd2, %rd1;
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; PTXC-NEXT: st.global.b32 [%rd2], %r1;
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; PTXC-NEXT: ret;
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; PTXO-LABEL: ptr_as_int(
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; PTXO: {
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; PTXO-NEXT: .reg .b32 %r<2>;
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; PTXO-NEXT: .reg .b64 %rd<2>;
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; PTXO-EMPTY:
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; PTXO-NEXT: // %bb.0:
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; PTXO-NEXT: ld.param.b64 %rd1, [ptr_as_int_param_0];
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; PTXO-NEXT: ld.param.b32 %r1, [ptr_as_int_param_1];
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; PTXO-NEXT: st.b32 [%rd1], %r1;
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; PTXO-NEXT: ret;
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%p = inttoptr i64 %i to ptr
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store i32 %v, ptr %p, align 4
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ret void
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}
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%struct.S = type { i64 }
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define ptx_kernel void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) {
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; IR-LABEL: define ptx_kernel void @ptr_as_int_aggr(
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; IR-SAME: ptr noundef readonly byval([[STRUCT_S:%.*]]) align 8 captures(none) [[S:%.*]], i32 noundef [[V:%.*]]) {
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; IR-NEXT: [[I:%.*]] = load i64, ptr [[S]], align 8
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; IR-NEXT: [[P:%.*]] = inttoptr i64 [[I]] to ptr
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; IR-NEXT: [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1)
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; IR-NEXT: [[P2:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr
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; IR-NEXT: store i32 [[V]], ptr [[P2]], align 4
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; IR-NEXT: ret void
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;
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; PTXC-LABEL: ptr_as_int_aggr(
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; PTXC: {
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; PTXC-NEXT: .reg .b32 %r<2>;
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; PTXC-NEXT: .reg .b64 %rd<3>;
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; PTXC-EMPTY:
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; PTXC-NEXT: // %bb.0:
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; PTXC-NEXT: ld.param.b32 %r1, [ptr_as_int_aggr_param_1];
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; PTXC-NEXT: ld.param.b64 %rd1, [ptr_as_int_aggr_param_0];
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; PTXC-NEXT: cvta.to.global.u64 %rd2, %rd1;
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; PTXC-NEXT: st.global.b32 [%rd2], %r1;
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; PTXC-NEXT: ret;
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; PTXO-LABEL: ptr_as_int_aggr(
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; PTXO: {
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; PTXO-NEXT: .reg .b32 %r<2>;
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; PTXO-NEXT: .reg .b64 %rd<2>;
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; PTXO-EMPTY:
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; PTXO-NEXT: // %bb.0:
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; PTXO-NEXT: ld.param.b32 %r1, [ptr_as_int_aggr_param_1];
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; PTXO-NEXT: ld.param.b64 %rd1, [ptr_as_int_aggr_param_0];
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; PTXO-NEXT: st.b32 [%rd1], %r1;
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; PTXO-NEXT: ret;
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%i = load i64, ptr %s, align 8
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%p = inttoptr i64 %i to ptr
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store i32 %v, ptr %p, align 4
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ret void
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}
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