derek.holloway
7502bf64a4
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33 lines
1.2 KiB
LLVM
33 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; Test to verify that NVPTX backend correctly handles conversion of constant
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; global vectors containing sub-byte sized elements.
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; RUN: llc < %s -O0 -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | FileCheck %s
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; RUN: %if ptxas-sm_100a && ptxas-isa-8.6 %{ llc < %s -O0 -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | %ptxas-verify -arch=sm_100a %}
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target triple = "nvptx-nvidia-cuda"
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; CHECK: .visible .global .align 1 .b8 test0[1] = {33};
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@test0 = local_unnamed_addr addrspace(1) constant <2 x i4> <i4 1, i4 2>, align 1
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define <2 x half> @foo() {
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; CHECK-LABEL: foo(
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; CHECK: {
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; CHECK-NEXT: .reg .b16 %rs<2>;
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.global.b8 %rs1, [test0];
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; CHECK-NEXT: {
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; CHECK-NEXT: .reg .b8 %e2m1x2_in;
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; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
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; CHECK-NEXT: cvt.rn.f16x2.e2m1x2 %r1, %e2m1x2_in;
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; CHECK-NEXT: }
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%ld = load i8, ptr addrspace(1) @test0, align 1
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%in = zext nneg i8 %ld to i16
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%val = call <2 x half> @llvm.nvvm.e2m1x2.to.f16x2.rn(i16 %in)
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ret <2 x half> %val
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}
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