derek.holloway
7502bf64a4
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41 lines
1.3 KiB
LLVM
41 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mcpu=sm_75 -mattr=+ptx70 | FileCheck %s
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; RUN: %if ptxas-sm_75 && ptxas-isa-7.0 %{ llc < %s -mcpu=sm_75 -mattr=+ptx70 | %ptxas-verify -arch=sm_75 %}
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target triple = "nvptx64-nvidia-cuda"
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define float @test1(float %in) local_unnamed_addr {
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; CHECK-LABEL: test1(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test1_param_0];
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; CHECK-NEXT: tanh.approx.f32 %r2, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%call = call afn float @llvm.tanh.f32(float %in)
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ret float %call
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}
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define half @test2(half %in) local_unnamed_addr {
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; CHECK-LABEL: test2(
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; CHECK: {
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; CHECK-NEXT: .reg .b16 %rs<3>;
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b16 %rs1, [test2_param_0];
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; CHECK-NEXT: cvt.f32.f16 %r1, %rs1;
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; CHECK-NEXT: tanh.approx.f32 %r2, %r1;
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; CHECK-NEXT: cvt.rn.f16.f32 %rs2, %r2;
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; CHECK-NEXT: st.param.b16 [func_retval0], %rs2;
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; CHECK-NEXT: ret;
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%call = call afn half @llvm.tanh.f16(half %in)
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ret half %call
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}
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declare float @llvm.tanh.f32(float)
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declare half @llvm.tanh.f16(half)
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