derek.holloway
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60 lines
2.0 KiB
LLVM
60 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; Optimized version which `xxleqv` and `vsubu` to generate vector of -1s to leverage the identity A - (-1) = A + 1.
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; Function for the vector type v2i64 `a + {1, 1}`
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define <2 x i64> @test_v2i64(<2 x i64> %a) {
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; CHECK-LABEL: test_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxleqv v3, v3, v3
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; CHECK-NEXT: vsubudm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%add = add <2 x i64> %a, splat (i64 1)
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ret <2 x i64> %add
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}
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; Function for the vector type v4i32 `a + {1, 1, 1, 1}`
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define <4 x i32> @test_v4i32(<4 x i32> %a) {
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; CHECK-LABEL: test_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxleqv v3, v3, v3
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; CHECK-NEXT: vsubuwm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%add = add <4 x i32> %a, splat (i32 1)
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ret <4 x i32> %add
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}
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; Function for the vector type v8i16 `a + {1, 1, 1, 1, 1, 1, 1, 1}`
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define <8 x i16> @test_v8i16(<8 x i16> %a) {
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; CHECK-LABEL: test_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxleqv v3, v3, v3
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; CHECK-NEXT: vsubuhm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%add = add <8 x i16> %a, splat (i16 1)
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ret <8 x i16> %add
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}
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; Function for the vector type v16i8 `a + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}`
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define <16 x i8> @test_16i8(<16 x i8> %a) {
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; CHECK-LABEL: test_16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxleqv v3, v3, v3
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; CHECK-NEXT: vsububm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%add = add <16 x i8> %a, splat (i8 1)
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ret <16 x i8> %add
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}
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