derek.holloway
7502bf64a4
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62 lines
2.0 KiB
LLVM
62 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s --check-prefixes=CHECK,CHECK32
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; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s --check-prefixes=CHECK,CHECK64
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define ptr @lower_args(ptr %_0, i32 %0, i32 %1, i32 %2, i32 %3, ptr %4, ptr %5, i64 %6, i24 %7) {
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; CHECK-LABEL: lower_args:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: blr
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entry:
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ret ptr %_0
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}
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define i32 @lower_args_withops_zeroext(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i24 %i) {
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; CHECK32-LABEL: lower_args_withops_zeroext:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: lwz r3, 56(r1)
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; CHECK32-NEXT: addi r3, r3, 255
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; CHECK32-NEXT: clrlwi r3, r3, 8
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; CHECK32-NEXT: blr
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;
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; CHECK64-LABEL: lower_args_withops_zeroext:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: lwz r3, 116(r1)
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; CHECK64-NEXT: addi r3, r3, 255
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; CHECK64-NEXT: clrldi r3, r3, 40
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; CHECK64-NEXT: blr
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entry:
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%0 = add i24 %i, 255
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%1 = zext i24 %0 to i32
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ret i32 %1
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}
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define i32 @lower_args_withops_signext(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i24 signext %i) {
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; CHECK32-LABEL: lower_args_withops_signext:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: lwz r3, 56(r1)
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; CHECK32-NEXT: slwi r3, r3, 8
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; CHECK32-NEXT: srawi r3, r3, 8
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; CHECK32-NEXT: slwi r3, r3, 8
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; CHECK32-NEXT: addi r3, r3, 22272
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; CHECK32-NEXT: srawi r3, r3, 8
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; CHECK32-NEXT: blr
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;
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; CHECK64-LABEL: lower_args_withops_signext:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: lwz r3, 116(r1)
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; CHECK64-NEXT: slwi r3, r3, 8
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; CHECK64-NEXT: srawi r3, r3, 8
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; CHECK64-NEXT: addi r3, r3, 87
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; CHECK64-NEXT: sldi r3, r3, 40
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; CHECK64-NEXT: sradi r3, r3, 40
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; CHECK64-NEXT: blr
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entry:
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%0 = add i24 %i, 87
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%1 = sext i24 %0 to i32
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ret i32 %1
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}
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