derek.holloway
7502bf64a4
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25 lines
1.1 KiB
LLVM
25 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+altivec | FileCheck %s
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define void @VXOR(ptr %P1, ptr %P2, ptr %P3) {
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%tmp = load <4 x float>, ptr %P3 ; <<4 x float>> [#uses=1]
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%tmp3 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]
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%tmp4 = fmul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4, ptr %P3
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store <4 x float> zeroinitializer, ptr %P1
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store <4 x i32> zeroinitializer, ptr %P2
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ret void
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}
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; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
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; to vmaddfp (so it would IEEE compliant with zero sign propagation).
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; CHECK: @VXOR
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; CHECK: vsplti
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; CHECK: vxor
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define void @VSPLTI(ptr %P2, ptr %P3) {
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store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), ptr %P2
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store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, ptr %P3
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ret void
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}
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; CHECK: @VSPLTI
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; CHECK: vsplti
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