derek.holloway
7502bf64a4
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142 lines
4.5 KiB
LLVM
142 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \
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; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr9 \
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; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
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define <16 x i8> @test_bcdcopysign(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_bcdcopysign:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bcdcpsgn. v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdsetsign_imm0(<16 x i8> %a) {
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; CHECK-LABEL: test_bcdsetsign_imm0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bcdsetsgn. v2, v2, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 0)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdsetsign_imm1(<16 x i8> %a) {
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; CHECK-LABEL: test_bcdsetsign_imm1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bcdsetsgn. v2, v2, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 1)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdshift_imm0(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdshift_imm0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcds. v2, v3, v2, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 0)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdshift_imm1(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdshift_imm1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcds. v2, v3, v2, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 1)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdshiftround_imm0(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdshiftround_imm0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcdsr. v2, v3, v2, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 0)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdshiftround_imm1(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdshiftround_imm1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcdsr. v2, v3, v2, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 1)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdtruncate_imm0(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdtruncate_imm0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcdtrunc. v2, v3, v2, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 0)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdtruncate_imm1(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdtruncate_imm1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcdtrunc. v2, v3, v2, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 1)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdunsignedtruncate(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdunsignedtruncate:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcdutrunc. v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8> %a, i32 %b)
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ret <16 x i8> %0
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}
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define <16 x i8> @test_bcdunsignedshift(<16 x i8> %a, i32 %b) {
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; CHECK-LABEL: test_bcdunsignedshift:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
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; CHECK-NEXT: bcdus. v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8> %a, i32 %b)
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ret <16 x i8> %0
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}
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declare <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8>, i32)
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declare <16 x i8> @llvm.ppc.bcdshift(<16 x i8>, i32, i32)
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declare <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8>, i32, i32)
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declare <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8>, i32, i32)
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declare <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8>, i32)
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declare <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8>, i32)
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