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TheRock/compiler/amd-llvm/llvm/test/CodeGen/PowerPC/mtvsrc-mfvscr-PPCVSXSwapRemoval.ll
derek.holloway 7502bf64a4
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2026-09-02 16:34:47 -07:00

38 lines
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LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -mcpu=pwr8 -O2 < %s | FileCheck %s
define void @test_mtvscr() {
; CHECK-LABEL: test_mtvscr:
; CHECK: # %bb.0: # %test_mtvscr_entry
; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 34, 0
; CHECK-NEXT: mtvscr 2
; CHECK-NEXT: blr
test_mtvscr_entry:
%0 = alloca <4 x i32>
%1 = load <4 x i32>, ptr %0
call void @llvm.ppc.altivec.mtvscr(<4 x i32> %1)
ret void
}
define void @test_mfvscr() {
; CHECK-LABEL: test_mfvscr:
; CHECK: # %bb.0: # %test_mfvscr_entry
; CHECK-NEXT: mfvscr 2
; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: stxvd2x 0, 0, 3
; CHECK-NEXT: blr
test_mfvscr_entry:
%0 = alloca <8 x i16>
%1 = call <8 x i16> @llvm.ppc.altivec.mfvscr()
store <8 x i16> %1, ptr %0
ret void
}
declare void @llvm.ppc.altivec.mtvscr(<4 x i32>)
declare <8 x i16> @llvm.ppc.altivec.mfvscr()