derek.holloway
7502bf64a4
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193 lines
7.0 KiB
LLVM
193 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple powerpc64 -mcpu=pwr10 < %s | FileCheck %s --check-prefix=BE
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; RUN: llc -mtriple powerpc64le -mcpu=pwr10 < %s | FileCheck %s --check-prefix=LE
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; RUN: llc -mtriple powerpc64le -mcpu=pwr10 -ppc-disable-perfect-shuffle=false < %s | FileCheck %s --check-prefix=LE
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; RUN: llc -mtriple powerpc64 -mcpu=pwr10 -ppc-disable-perfect-shuffle=false < %s | FileCheck %s --check-prefix=BE-ENABLE
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; TODO: Fix the worse codegen when disabling perfect shuffle
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define <4 x float> @shuffle1(<16 x i8> %v1, <16 x i8> %v2) {
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; BE-LABEL: shuffle1:
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; BE: # %bb.0:
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; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; BE-NEXT: lxv 36, 0(3)
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; BE-NEXT: vperm 2, 2, 3, 4
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; BE-NEXT: blr
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;
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; LE-LABEL: shuffle1:
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; LE: # %bb.0:
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; LE-NEXT: vpkudum 2, 3, 2
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; LE-NEXT: blr
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;
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; BE-ENABLE-LABEL: shuffle1:
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; BE-ENABLE: # %bb.0:
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; BE-ENABLE-NEXT: xxmrglw 0, 34, 35
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; BE-ENABLE-NEXT: xxmrghw 1, 34, 35
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; BE-ENABLE-NEXT: xxmrghw 34, 1, 0
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; BE-ENABLE-NEXT: blr
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%shuf = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
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%cast = bitcast <16 x i8> %shuf to <4 x float>
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ret <4 x float> %cast
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}
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define <4 x float> @shuffle2(<16 x i8> %v1, <16 x i8> %v2) {
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; BE-LABEL: shuffle2:
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; BE: # %bb.0:
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; BE-NEXT: vpkudum 2, 2, 3
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; BE-NEXT: blr
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;
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; LE-LABEL: shuffle2:
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; LE: # %bb.0:
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; LE-NEXT: plxv 36, .LCPI1_0@PCREL(0), 1
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; LE-NEXT: vperm 2, 3, 2, 4
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; LE-NEXT: blr
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;
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; BE-ENABLE-LABEL: shuffle2:
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; BE-ENABLE: # %bb.0:
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; BE-ENABLE-NEXT: vpkudum 2, 2, 3
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; BE-ENABLE-NEXT: blr
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%shuf = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
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%cast = bitcast <16 x i8> %shuf to <4 x float>
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ret <4 x float> %cast
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}
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define <4 x float> @shuffle3(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x i8> %v4) {
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; BE-LABEL: shuffle3:
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; BE: # %bb.0:
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; BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; BE-NEXT: addi 3, 3, .LCPI2_0@toc@l
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; BE-NEXT: lxv 32, 0(3)
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; BE-NEXT: vperm 2, 2, 3, 0
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; BE-NEXT: vperm 3, 4, 5, 0
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; BE-NEXT: xvaddsp 34, 34, 35
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; BE-NEXT: blr
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;
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; LE-LABEL: shuffle3:
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; LE: # %bb.0:
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; LE-NEXT: vpkudum 2, 3, 2
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; LE-NEXT: vpkudum 3, 5, 4
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; LE-NEXT: xvaddsp 34, 34, 35
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; LE-NEXT: blr
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;
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; BE-ENABLE-LABEL: shuffle3:
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; BE-ENABLE: # %bb.0:
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; BE-ENABLE-NEXT: xxmrglw 0, 34, 35
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; BE-ENABLE-NEXT: xxmrghw 1, 34, 35
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; BE-ENABLE-NEXT: xxmrghw 34, 1, 0
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; BE-ENABLE-NEXT: xxmrglw 0, 36, 37
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; BE-ENABLE-NEXT: xxmrghw 1, 36, 37
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; BE-ENABLE-NEXT: xxmrghw 35, 1, 0
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; BE-ENABLE-NEXT: xvaddsp 34, 34, 35
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; BE-ENABLE-NEXT: blr
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%shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
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%shuf2 = shufflevector <16 x i8> %v3, <16 x i8> %v4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
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%cast1 = bitcast <16 x i8> %shuf1 to <4 x float>
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%cast2 = bitcast <16 x i8> %shuf2 to <4 x float>
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%add = fadd <4 x float> %cast1, %cast2
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ret <4 x float> %add
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}
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define <4 x float> @shuffle4(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x i8> %v4) {
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; BE-LABEL: shuffle4:
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; BE: # %bb.0:
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; BE-NEXT: vpkudum 2, 2, 3
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; BE-NEXT: vpkudum 3, 4, 5
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; BE-NEXT: xvaddsp 34, 34, 35
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; BE-NEXT: blr
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;
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; LE-LABEL: shuffle4:
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; LE: # %bb.0:
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; LE-NEXT: plxv 32, .LCPI3_0@PCREL(0), 1
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; LE-NEXT: vperm 2, 3, 2, 0
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; LE-NEXT: vperm 3, 5, 4, 0
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; LE-NEXT: xvaddsp 34, 34, 35
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; LE-NEXT: blr
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;
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; BE-ENABLE-LABEL: shuffle4:
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; BE-ENABLE: # %bb.0:
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; BE-ENABLE-NEXT: vpkudum 2, 2, 3
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; BE-ENABLE-NEXT: vpkudum 3, 4, 5
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; BE-ENABLE-NEXT: xvaddsp 34, 34, 35
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; BE-ENABLE-NEXT: blr
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%shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
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%shuf2 = shufflevector <16 x i8> %v3, <16 x i8> %v4, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>
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%cast1 = bitcast <16 x i8> %shuf1 to <4 x float>
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%cast2 = bitcast <16 x i8> %shuf2 to <4 x float>
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%add = fadd <4 x float> %cast1, %cast2
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ret <4 x float> %add
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}
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define <4 x float> @shuffle5(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3, <16 x i8> %v4) {
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; BE-LABEL: shuffle5:
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; BE: # %bb.0: # %entry
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; BE-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; BE-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; BE-NEXT: lxv 32, 0(3)
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; BE-NEXT: li 3, 8
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; BE-NEXT: vextublx 3, 3, 2
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; BE-NEXT: andi. 3, 3, 255
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; BE-NEXT: vperm 3, 2, 3, 0
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; BE-NEXT: vmr 2, 3
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; BE-NEXT: beq 0, .LBB4_2
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; BE-NEXT: # %bb.1: # %exit
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; BE-NEXT: xvaddsp 34, 35, 34
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; BE-NEXT: blr
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; BE-NEXT: .LBB4_2: # %second
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; BE-NEXT: vperm 2, 4, 5, 0
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; BE-NEXT: xvaddsp 34, 35, 34
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; BE-NEXT: blr
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;
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; LE-LABEL: shuffle5:
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; LE: # %bb.0: # %entry
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; LE-NEXT: vpkudum 3, 3, 2
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; LE-NEXT: li 3, 8
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; LE-NEXT: vextubrx 3, 3, 2
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; LE-NEXT: vmr 2, 3
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; LE-NEXT: andi. 3, 3, 255
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; LE-NEXT: beq 0, .LBB4_2
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; LE-NEXT: # %bb.1: # %exit
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; LE-NEXT: xvaddsp 34, 35, 34
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; LE-NEXT: blr
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; LE-NEXT: .LBB4_2: # %second
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; LE-NEXT: vpkudum 2, 5, 4
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; LE-NEXT: xvaddsp 34, 35, 34
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; LE-NEXT: blr
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;
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; BE-ENABLE-LABEL: shuffle5:
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; BE-ENABLE: # %bb.0: # %entry
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; BE-ENABLE-NEXT: xxmrglw 0, 34, 35
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; BE-ENABLE-NEXT: xxmrghw 1, 34, 35
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; BE-ENABLE-NEXT: li 3, 8
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; BE-ENABLE-NEXT: vextublx 3, 3, 2
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; BE-ENABLE-NEXT: xxmrghw 0, 1, 0
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; BE-ENABLE-NEXT: andi. 3, 3, 255
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; BE-ENABLE-NEXT: xxlor 35, 0, 0
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; BE-ENABLE-NEXT: beq 0, .LBB4_2
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; BE-ENABLE-NEXT: # %bb.1: # %exit
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; BE-ENABLE-NEXT: xvaddsp 34, 35, 0
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; BE-ENABLE-NEXT: blr
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; BE-ENABLE-NEXT: .LBB4_2: # %second
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; BE-ENABLE-NEXT: xxmrglw 0, 36, 37
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; BE-ENABLE-NEXT: xxmrghw 1, 36, 37
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; BE-ENABLE-NEXT: xxmrghw 0, 1, 0
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; BE-ENABLE-NEXT: xvaddsp 34, 35, 0
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; BE-ENABLE-NEXT: blr
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entry:
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%shuf1 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
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%fetch = extractelement <16 x i8> %shuf1, i32 4
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%icmp = icmp eq i8 %fetch, 0
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br i1 %icmp, label %second, label %exit
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second:
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%shufs = shufflevector <16 x i8> %v3, <16 x i8> %v4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>
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br label %exit
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exit:
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%shuf2 = phi <16 x i8> [%shuf1, %entry], [%shufs, %second]
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%cast1 = bitcast <16 x i8> %shuf1 to <4 x float>
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%cast2 = bitcast <16 x i8> %shuf2 to <4 x float>
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%add = fadd <4 x float> %cast1, %cast2
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ret <4 x float> %add
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}
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