derek.holloway
7502bf64a4
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110 lines
3.0 KiB
LLVM
110 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE
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define void @test1(<4 x i32> %A, ptr %a) {
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; CHECK-LE-LABEL: test1:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: stxvrwx v2, 0, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-BE-NEXT: stfiwx f0, 0, r5
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %A, i32 0
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store i32 %vecext, ptr %a, align 4
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ret void
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}
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define void @test2(<4 x float> %A, ptr %a) {
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; CHECK-LE-LABEL: test2:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: stxvrwx v2, 0, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
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; CHECK-BE-NEXT: stfiwx f0, 0, r5
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x float> %A, i32 0
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store float %vecext, ptr %a, align 4
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ret void
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}
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define void @test3(<2 x double> %A, ptr %a) {
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; CHECK-LE-LABEL: test3:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: stxvrdx v2, 0, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: stxsd v2, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <2 x double> %A, i32 0
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store double %vecext, ptr %a, align 8
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ret void
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}
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define void @test4(<2 x i64> %A, ptr %a) {
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; CHECK-LE-LABEL: test4:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: stxvrdx v2, 0, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: stxsd v2, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <2 x i64> %A, i32 0
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store i64 %vecext, ptr %a, align 8
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ret void
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}
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define void @test5(<8 x i16> %A, ptr %a) {
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; CHECK-LE-LABEL: test5:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: stxvrhx v2, 0, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
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; CHECK-BE-NEXT: stxsihx v2, 0, r5
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %A, i32 0
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store i16 %vecext, ptr %a, align 2
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ret void
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}
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define void @test6(<16 x i8> %A, ptr %a) {
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; CHECK-LE-LABEL: test6:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: stxvrbx v2, 0, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test6:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vsldoi v2, v2, v2, 9
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; CHECK-BE-NEXT: stxsibx v2, 0, r5
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %A, i32 0
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store i8 %vecext, ptr %a, align 1
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ret void
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}
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