derek.holloway
7502bf64a4
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150 lines
4.4 KiB
LLVM
150 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = local_unnamed_addr global i64 0, align 8
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subc r3, r4, r3
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; CHECK-NEXT: adde r3, r6, r5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subc r3, r4, r3
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; CHECK-NEXT: adde r3, r6, r5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; FIXME
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_z(i64 %a) {
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; CHECK-LABEL: test_igtsll_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: nor r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsll_sext_z(i64 %a) {
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; CHECK-LABEL: test_igtsll_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: nor r3, r4, r3
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subc r3, r4, r3
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: adde r3, r6, r5
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, ptr @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igtsll_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subc r3, r4, r3
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: adde r3, r6, r5
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, ptr @glob, align 8
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ret void
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}
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; FIXME
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_z_store(i64 %a) {
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; CHECK-LABEL: test_igtsll_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: nor r3, r4, r3
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, ptr @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_igtsll_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: nor r3, r4, r3
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, 0
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, ptr @glob, align 8
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ret void
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}
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