derek.holloway
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150 lines
4.2 KiB
LLVM
150 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
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; RUN: FileCheck %s --check-prefix=AIX
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; Test for load/store to/from v4i32.
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define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
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; CHECK-LABEL: testLXVRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvrl v2, r3, r4
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvrl v2, r3, r4
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; AIX-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrl(ptr %a, i64 %b)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.vsx.lxvrl(ptr, i64)
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define <4 x i32> @testLXVRLL(ptr %a, i64 %b) {
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; CHECK-LABEL: testLXVRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvrll v2, r3, r4
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvrll v2, r3, r4
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; AIX-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrll(ptr %a, i64 %b)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
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define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
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; CHECK-LABEL: testSTXVRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stxvrl v2, r5, r6
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: stxvrl v2, r3, r4
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; AIX-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
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define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
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; CHECK-LABEL: testSTXVRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stxvrll v2, r5, r6
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: stxvrll v2, r3, r4
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; AIX-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
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; Test for load/store vectore pair.
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define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
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; CHECK-LABEL: testLXVPRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvprl vsp34, r4, r5
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; CHECK-NEXT: stxvp vsp34, 0(r3)
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVPRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvprl vsp34, r4, r5
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; AIX-NEXT: stxvp vsp34, 0(r3)
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; AIX-NEXT: blr
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entry:
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%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
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ret <256 x i1> %0
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}
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declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
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define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
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; CHECK-LABEL: testLXVPRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvprll vsp34, r4, r5
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; CHECK-NEXT: stxvp vsp34, 0(r3)
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVPRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvprll vsp34, r4, r5
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; AIX-NEXT: stxvp vsp34, 0(r3)
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; AIX-NEXT: blr
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entry:
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%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
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ret <256 x i1> %0
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}
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declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
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define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
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; CHECK-LABEL: testSTXVPRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvp vsp34, 0(r3)
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; CHECK-NEXT: stxvprl vsp34, r4, r5
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVPRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvp vsp34, 0(r3)
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; AIX-NEXT: stxvprl vsp34, r4, r5
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; AIX-NEXT: blr
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entry:
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%0 = load <256 x i1>, ptr %v, align 32
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tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
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define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
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; CHECK-LABEL: testSTXVPRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvp vsp34, 0(r3)
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; CHECK-NEXT: stxvprll vsp34, r4, r5
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVPRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvp vsp34, 0(r3)
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; AIX-NEXT: stxvprll vsp34, r4, r5
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; AIX-NEXT: blr
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entry:
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%0 = load <256 x i1>, ptr %v, align 32
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tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvprll(<256 x i1>, ptr, i64)
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