derek.holloway
7502bf64a4
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320 lines
9.1 KiB
LLVM
320 lines
9.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV32
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; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV64
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define i2 @bitreverse_i2(i2 %x) {
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; RV32-LABEL: bitreverse_i2:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a0, 1
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; RV32-NEXT: andi a0, a0, 3
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; RV32-NEXT: andi a1, a1, 2
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; RV32-NEXT: srli a0, a0, 1
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bitreverse_i2:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a0, 1
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; RV64-NEXT: andi a0, a0, 3
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; RV64-NEXT: andi a1, a1, 2
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; RV64-NEXT: srli a0, a0, 1
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: ret
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%rev = call i2 @llvm.bitreverse.i2(i2 %x)
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ret i2 %rev
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}
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define i3 @bitreverse_i3(i3 %x) {
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; RV32-LABEL: bitreverse_i3:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a0, 2
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; RV32-NEXT: andi a0, a0, 7
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; RV32-NEXT: andi a1, a1, 4
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; RV32-NEXT: andi a2, a0, 2
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: srli a0, a0, 2
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bitreverse_i3:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a0, 2
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; RV64-NEXT: andi a0, a0, 7
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; RV64-NEXT: andi a1, a1, 4
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; RV64-NEXT: andi a2, a0, 2
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; RV64-NEXT: or a1, a1, a2
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; RV64-NEXT: srli a0, a0, 2
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: ret
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%rev = call i3 @llvm.bitreverse.i3(i3 %x)
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ret i3 %rev
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}
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define i4 @bitreverse_i4(i4 %x) {
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; RV32-LABEL: bitreverse_i4:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a0, 3
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; RV32-NEXT: slli a2, a0, 1
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; RV32-NEXT: andi a0, a0, 15
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; RV32-NEXT: andi a1, a1, 8
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; RV32-NEXT: andi a2, a2, 4
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: srli a2, a0, 1
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; RV32-NEXT: andi a2, a2, 2
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: srli a0, a0, 3
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bitreverse_i4:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a0, 3
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; RV64-NEXT: slli a2, a0, 1
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; RV64-NEXT: andi a0, a0, 15
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; RV64-NEXT: andi a1, a1, 8
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; RV64-NEXT: andi a2, a2, 4
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; RV64-NEXT: or a1, a1, a2
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; RV64-NEXT: srli a2, a0, 1
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; RV64-NEXT: andi a2, a2, 2
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; RV64-NEXT: or a1, a1, a2
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; RV64-NEXT: srli a0, a0, 3
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: ret
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%rev = call i4 @llvm.bitreverse.i4(i4 %x)
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ret i4 %rev
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}
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define i7 @bitreverse_i7(i7 %x) {
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; RV32-LABEL: bitreverse_i7:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a0, 6
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; RV32-NEXT: slli a2, a0, 4
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; RV32-NEXT: slli a3, a0, 2
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; RV32-NEXT: andi a0, a0, 127
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; RV32-NEXT: andi a1, a1, 64
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; RV32-NEXT: andi a2, a2, 32
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; RV32-NEXT: andi a3, a3, 16
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: andi a2, a0, 8
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; RV32-NEXT: or a2, a3, a2
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; RV32-NEXT: srli a3, a0, 2
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: srli a2, a0, 4
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; RV32-NEXT: andi a3, a3, 4
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; RV32-NEXT: andi a2, a2, 2
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; RV32-NEXT: or a2, a3, a2
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: srli a0, a0, 6
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bitreverse_i7:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a0, 6
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; RV64-NEXT: slli a2, a0, 4
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; RV64-NEXT: slli a3, a0, 2
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; RV64-NEXT: andi a0, a0, 127
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; RV64-NEXT: andi a1, a1, 64
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; RV64-NEXT: andi a2, a2, 32
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; RV64-NEXT: andi a3, a3, 16
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; RV64-NEXT: or a1, a1, a2
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; RV64-NEXT: andi a2, a0, 8
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; RV64-NEXT: or a2, a3, a2
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; RV64-NEXT: srli a3, a0, 2
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; RV64-NEXT: or a1, a1, a2
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; RV64-NEXT: srli a2, a0, 4
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; RV64-NEXT: andi a3, a3, 4
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; RV64-NEXT: andi a2, a2, 2
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; RV64-NEXT: or a2, a3, a2
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; RV64-NEXT: or a1, a1, a2
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; RV64-NEXT: srli a0, a0, 6
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: ret
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%rev = call i7 @llvm.bitreverse.i7(i7 %x)
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ret i7 %rev
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}
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define i24 @bitreverse_i24(i24 %x) {
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; RV32-LABEL: bitreverse_i24:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a0, 16
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; RV32-NEXT: lui a2, 4096
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; RV32-NEXT: lui a3, 1048335
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; RV32-NEXT: addi a2, a2, -1
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; RV32-NEXT: addi a3, a3, 240
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; RV32-NEXT: and a0, a0, a2
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; RV32-NEXT: srli a0, a0, 16
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; RV32-NEXT: or a0, a0, a1
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; RV32-NEXT: and a1, a3, a2
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; RV32-NEXT: and a1, a0, a1
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; RV32-NEXT: slli a0, a0, 4
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; RV32-NEXT: and a0, a0, a3
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; RV32-NEXT: lui a3, 1047757
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; RV32-NEXT: addi a3, a3, -820
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; RV32-NEXT: srli a1, a1, 4
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: and a1, a3, a2
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; RV32-NEXT: and a1, a0, a1
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; RV32-NEXT: slli a0, a0, 2
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; RV32-NEXT: and a0, a0, a3
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; RV32-NEXT: lui a3, 1047211
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; RV32-NEXT: addi a3, a3, -1366
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; RV32-NEXT: and a2, a3, a2
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; RV32-NEXT: srli a1, a1, 2
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: and a2, a0, a2
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; RV32-NEXT: slli a0, a0, 1
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; RV32-NEXT: srli a2, a2, 1
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; RV32-NEXT: and a0, a0, a3
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; RV32-NEXT: or a0, a2, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bitreverse_i24:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a0, 16
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; RV64-NEXT: lui a2, 4096
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; RV64-NEXT: lui a3, 1048335
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; RV64-NEXT: addi a2, a2, -1
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; RV64-NEXT: addi a3, a3, 240
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; RV64-NEXT: and a0, a0, a2
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; RV64-NEXT: srli a0, a0, 16
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; RV64-NEXT: or a0, a0, a1
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; RV64-NEXT: and a1, a3, a2
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; RV64-NEXT: and a1, a0, a1
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; RV64-NEXT: slli a0, a0, 4
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; RV64-NEXT: and a0, a0, a3
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; RV64-NEXT: lui a3, 1047757
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; RV64-NEXT: addi a3, a3, -820
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; RV64-NEXT: srli a1, a1, 4
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: and a1, a3, a2
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; RV64-NEXT: and a1, a0, a1
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; RV64-NEXT: slli a0, a0, 2
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; RV64-NEXT: and a0, a0, a3
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; RV64-NEXT: lui a3, 1047211
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; RV64-NEXT: addi a3, a3, -1366
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; RV64-NEXT: and a2, a3, a2
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; RV64-NEXT: srli a1, a1, 2
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: and a2, a0, a2
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; RV64-NEXT: slli a0, a0, 1
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; RV64-NEXT: srli a2, a2, 1
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; RV64-NEXT: and a0, a0, a3
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; RV64-NEXT: or a0, a2, a0
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; RV64-NEXT: ret
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%rev = call i24 @llvm.bitreverse.i24(i24 %x)
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ret i24 %rev
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}
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define i2 @test_ctpop_i2(i2 %a) {
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; RV32-LABEL: test_ctpop_i2:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: andi a0, a0, 3
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; RV32-NEXT: srli a1, a0, 1
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: zext.b a1, a0
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; RV32-NEXT: srli a1, a1, 2
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; RV32-NEXT: andi a1, a1, 51
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; RV32-NEXT: andi a0, a0, 51
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: srli a1, a0, 4
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: andi a0, a0, 15
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; RV32-NEXT: li a1, 1
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; RV32-NEXT: call __mulsi3
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; RV32-NEXT: zext.b a0, a0
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: .cfi_restore ra
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_ctpop_i2:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: andi a0, a0, 3
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; RV64-NEXT: srli a1, a0, 1
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: zext.b a1, a0
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; RV64-NEXT: srli a1, a1, 2
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; RV64-NEXT: andi a1, a1, 51
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; RV64-NEXT: andi a0, a0, 51
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: srli a1, a0, 4
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: andi a0, a0, 15
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; RV64-NEXT: li a1, 1
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; RV64-NEXT: call __muldi3
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; RV64-NEXT: zext.b a0, a0
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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%1 = call i2 @llvm.ctpop.i2(i2 %a)
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ret i2 %1
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}
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define i11 @test_ctpop_i11(i11 %a) {
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; RV32-LABEL: test_ctpop_i11:
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; RV32: # %bb.0:
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; RV32-NEXT: andi a0, a0, 2047
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; RV32-NEXT: lui a1, 5
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; RV32-NEXT: srli a2, a0, 1
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; RV32-NEXT: addi a1, a1, 1365
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; RV32-NEXT: and a1, a2, a1
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; RV32-NEXT: lui a2, 3
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; RV32-NEXT: addi a2, a2, 819
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: slli a1, a0, 16
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; RV32-NEXT: and a0, a0, a2
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; RV32-NEXT: srli a1, a1, 16
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; RV32-NEXT: srli a1, a1, 2
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; RV32-NEXT: and a1, a1, a2
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; RV32-NEXT: lui a2, 1
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: srli a1, a0, 4
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: addi a1, a2, -241
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; RV32-NEXT: and a0, a0, a1
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; RV32-NEXT: srli a1, a0, 8
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: zext.b a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_ctpop_i11:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, 2047
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; RV64-NEXT: lui a1, 5
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; RV64-NEXT: srli a2, a0, 1
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; RV64-NEXT: addi a1, a1, 1365
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; RV64-NEXT: and a1, a2, a1
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; RV64-NEXT: lui a2, 3
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; RV64-NEXT: addi a2, a2, 819
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: slli a1, a0, 48
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; RV64-NEXT: and a0, a0, a2
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; RV64-NEXT: srli a1, a1, 48
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; RV64-NEXT: srli a1, a1, 2
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; RV64-NEXT: and a1, a1, a2
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; RV64-NEXT: lui a2, 1
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: srli a1, a0, 4
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: addi a1, a2, -241
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; RV64-NEXT: and a0, a0, a1
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; RV64-NEXT: srli a1, a0, 8
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: zext.b a0, a0
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; RV64-NEXT: ret
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%1 = call i11 @llvm.ctpop.i11(i11 %a)
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ret i11 %1
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}
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