TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/merge-unmerge-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN:   | FileCheck --check-prefix=RV32 %s

---
name:            merge_i32
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: merge_i32
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; RV32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
    ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; RV32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)
    ; RV32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ASSERT_ZEXT]], [[SHL]]
    ; RV32-NEXT: $x10 = COPY [[OR]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = G_ASSERT_ZEXT %0, 16
    %2:_(s16) = G_TRUNC %1(s32)
    %3:_(s32) = G_MERGE_VALUES %2(s16), %2(s16)
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10
...
---
name:            merge_i64
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: merge_i64
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; RV32-NEXT: $x10 = COPY [[COPY]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s64) = G_MERGE_VALUES %0(s32), %0(s32)
    %2:_(s32) = G_TRUNC %1(s64)
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10
...
---
name:            merge_i128
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: merge_i128
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; RV32-NEXT: $x10 = COPY [[COPY]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %1:_(s32) = COPY $x10
    %2:_(s64) = G_ZEXT %1(s32)
    %0:_(s128) = G_MERGE_VALUES %2(s64), %2(s64)
    %3:_(s32) = G_TRUNC %0(s128)
    $x10 = COPY %3(s32)
    PseudoRET implicit $x10
...
---
name:            unmerge_i32
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: unmerge_i32
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; RV32-NEXT: $x10 = COPY [[AND]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0(s32)
    %4:_(s32) = G_ZEXT %2(s16)
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10
...
---
name:            unmerge_i64
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: unmerge_i64
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; RV32-NEXT: $x10 = COPY [[COPY]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10
...
---
name:            unmerge_i128
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: unmerge_i128
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; RV32-NEXT: $x10 = COPY [[C]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s128) = G_ZEXT %0(s32)
    %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128)
    %4:_(s32) = G_TRUNC %3(s64)
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10
...
---
name:            unmerge_i256
body:             |
  bb.0.entry:
    liveins: $x10
    ; RV32-LABEL: name: unmerge_i256
    ; RV32: liveins: $x10
    ; RV32-NEXT: {{  $}}
    ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; RV32-NEXT: $x10 = COPY [[COPY]](s32)
    ; RV32-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s256) = G_ZEXT %0(s32)
    %2:_(s128), %3:_(s128) = G_UNMERGE_VALUES %1(s256)
    %4:_(s32) = G_TRUNC %2(s128)
    $x10 = COPY %4(s32)
    PseudoRET implicit $x10
...