derek.holloway
7502bf64a4
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195 lines
5.1 KiB
LLVM
195 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I
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; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I
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define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; RV32I-LABEL: ucmp.8.8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a1, a0
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: sub a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; RV32I-LABEL: ucmp.8.16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a1, a0
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: sub a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: ucmp.8.32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a1, a0
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: sub a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: ucmp.8.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a3, a1
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; RV32I-NEXT: sltu a0, a1, a3
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; RV32I-NEXT: sub a0, a4, a0
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: sltu a4, a2, a0
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: sub a0, a4, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: sub a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: ucmp.32.32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a1, a0
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: subw a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
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; RV32I-LABEL: ucmp.32.32_sext:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a1, a0
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.32_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: subw a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {
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; RV32I-LABEL: ucmp.32.32_zext:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a1, a0
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.32_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: subw a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: ucmp.32.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB7_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a3, a1
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; RV32I-NEXT: sltu a0, a1, a3
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; RV32I-NEXT: sub a0, a4, a0
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB7_2:
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; RV32I-NEXT: sltu a4, a2, a0
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: sub a0, a4, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: subw a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: ucmp.64.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB8_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a3, a1
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; RV32I-NEXT: sltu a1, a1, a3
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; RV32I-NEXT: j .LBB8_3
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; RV32I-NEXT: .LBB8_2:
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; RV32I-NEXT: sltu a4, a2, a0
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; RV32I-NEXT: sltu a1, a0, a2
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; RV32I-NEXT: .LBB8_3:
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; RV32I-NEXT: sub a0, a4, a1
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; RV32I-NEXT: sltu a1, a4, a1
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; RV32I-NEXT: neg a1, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.64.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a1, a0
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: sub a0, a2, a0
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; RV64I-NEXT: ret
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%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
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ret i64 %1
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}
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