derek.holloway
7502bf64a4
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264 lines
6.4 KiB
LLVM
264 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,RV64
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define i1 @test1(i64 %x) {
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; RV32-LABEL: test1:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a2, a1, 2
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; RV32-NEXT: srli a0, a0, 30
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; RV32-NEXT: srai a1, a1, 30
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; RV32-NEXT: or a0, a0, a2
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; RV32-NEXT: xori a0, a0, -2
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; RV32-NEXT: not a1, a1
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; RV32-NEXT: or a0, a0, a1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test1:
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; RV64: # %bb.0:
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; RV64-NEXT: srai a0, a0, 30
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; RV64-NEXT: addi a0, a0, 2
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, -1073741824
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%b = icmp eq i64 %a, -2147483648
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ret i1 %b
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}
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define i1 @test2(i32 signext %x) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a0, a0, 30
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%a = and i32 %x, -1073741824
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%b = icmp eq i32 %a, 0
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ret i1 %b
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}
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define i1 @test3(i32 signext %x) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a0, a0, 29
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%a = and i32 %x, -536870912
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%b = icmp ne i32 %a, 0
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ret i1 %b
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}
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define i1 @test4(i64 %x) {
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; RV32-LABEL: test4:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a1, a1, 14
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; RV32-NEXT: seqz a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test4:
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; RV64: # %bb.0:
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; RV64-NEXT: srli a0, a0, 46
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, -70368744177664
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%b = icmp eq i64 %a, 0
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ret i1 %b
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}
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define i1 @test5(i64 %x) {
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; RV32-LABEL: test5:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a0, a0, 29
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test5:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 29
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, u0xE0000000
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%b = icmp eq i64 %a, 0
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ret i1 %b
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}
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define i1 @test6(i64 %x) {
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; RV32-LABEL: test6:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a0, a0, 29
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; RV32-NEXT: snez a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test6:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 29
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; RV64-NEXT: snez a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, u0xE0000000
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%b = icmp ne i64 %a, 0
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ret i1 %b
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}
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define i1 @test7(i64 %x) {
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; RV32-LABEL: test7:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a0, a0, 29
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; RV32-NEXT: addi a0, a0, -6
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test7:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 29
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; RV64-NEXT: addi a0, a0, 2
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, u0xE0000000
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%b = icmp eq i64 %a, u0xC0000000
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ret i1 %b
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}
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define i1 @test8(i64 %x) {
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; RV32-LABEL: test8:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a0, a0, 20
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; RV32-NEXT: xori a0, a0, -2048
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; RV32-NEXT: snez a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test8:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 20
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; RV64-NEXT: xori a0, a0, -2048
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; RV64-NEXT: snez a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, u0xFFF00000
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%b = icmp ne i64 %a, u0x80000000
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ret i1 %b
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}
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define i1 @test9(i64 %x) {
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; RV32-LABEL: test9:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a0, a0, 16
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; RV32-NEXT: addi a0, a0, -2048
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test9:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 16
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; RV64-NEXT: addi a0, a0, -2048
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, u0xFFFF0000
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%b = icmp eq i64 %a, u0x08000000
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ret i1 %b
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}
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; Make sure the and constant doesn't get converted to an opaque constant by
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; ConstantHoisting. If it's an opaque constant, we'll have addi -16 and addi 15.
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define i64 @test10(i64 %0) #0 {
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; RV32-LABEL: test10:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: andi a0, a0, -16
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; RV32-NEXT: snez a0, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test10:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: sraiw a0, a0, 4
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; RV64-NEXT: snez a0, a0
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; RV64-NEXT: ret
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entry:
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%1 = add nuw nsw i64 %0, u0xffffffff
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%2 = and i64 %1, u0xfffffff0
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%3 = icmp ne i64 %2, 0
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%4 = zext i1 %3 to i64
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ret i64 %4
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}
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; Make sure the and constant doesn't get converted to an opaque constant by
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; ConstantHoisting. If it's an opaque constant, we'll have addi -16 and addi 15.
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define i64 @test11(i64 %0) #0 {
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; RV32-LABEL: test11:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: srai a0, a0, 4
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; RV32-NEXT: addi a0, a0, 1621
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test11:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi a0, a0, -1
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; RV64-NEXT: sraiw a0, a0, 4
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; RV64-NEXT: addi a0, a0, 1621
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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entry:
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%1 = add nuw nsw i64 %0, u0xffffffff
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%2 = and i64 %1, u0xfffffff0
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%3 = icmp eq i64 %2, u0xffff9ab0
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%4 = zext i1 %3 to i64
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ret i64 %4
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}
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; Make sure the and constant doesn't get converted to an opaque constant by
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; ConstantHoisting. If it's an opaque constant we'll end up with constant
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; materialization sequences on RV64.
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define i64 @test12(i64 %0) #0 {
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; RV32-LABEL: test12:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi a0, a0, -3
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test12:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi a0, a0, -16
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; RV64-NEXT: addiw a0, a0, 13
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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entry:
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%1 = add nuw nsw i64 %0, u0xfffffff0
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%2 = and i64 %1, u0xffffffff
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%3 = icmp eq i64 %2, u0xfffffff3
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%4 = zext i1 %3 to i64
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ret i64 %4
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}
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; Make sure the and constant doesn't get converted to an opaque constant by
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; ConstantHoisting.
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define i64 @test13(i64 %0) #0 {
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; RV32-LABEL: test13:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lui a1, 524288
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; RV32-NEXT: addi a1, a1, 15
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: srli a0, a0, 31
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test13:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: lui a1, 524288
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; RV64-NEXT: addi a1, a1, -15
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: sraiw a0, a0, 31
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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entry:
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%1 = add nuw nsw i64 %0, u0x8000000f
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%2 = and i64 %1, u0x80000000
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%3 = icmp eq i64 %2, 0
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%4 = zext i1 %3 to i64
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ret i64 %4
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}
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