derek.holloway
7502bf64a4
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98 lines
2.4 KiB
LLVM
98 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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define i32 @and_0xfff_shl_2(i32 %x) {
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; RV32I-LABEL: and_0xfff_shl_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 18
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_0xfff_shl_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 50
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; RV64I-NEXT: ret
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%a = and i32 %x, 4095
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%s = shl i32 %a, 2
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ret i32 %s
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}
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define i32 @and_0x7ff_shl_2(i32 %x) {
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; RV32I-LABEL: and_0x7ff_shl_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 2047
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; RV32I-NEXT: slli a0, a0, 2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_0x7ff_shl_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 2047
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: ret
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%a = and i32 %x, 2047
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%s = shl i32 %a, 2
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ret i32 %s
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}
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define i64 @and_0xffffffff_shl_2(i64 %x) {
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; RV32I-LABEL: and_0xffffffff_shl_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a0, 2
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; RV32I-NEXT: srli a1, a0, 30
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_0xffffffff_shl_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 30
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; RV64I-NEXT: ret
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%a = and i64 %x, 4294967295
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%s = shl i64 %a, 2
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ret i64 %s
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}
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define i32 @and_0xfff_shl_2_multi_use(i32 %x) {
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; RV32I-LABEL: and_0xfff_shl_2_multi_use:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 20
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; RV32I-NEXT: slli a1, a0, 2
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_0xfff_shl_2_multi_use:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 52
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; RV64I-NEXT: slli a1, a0, 2
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i32 %x, 4095
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%s = shl i32 %a, 2
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%r = add i32 %a, %s
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ret i32 %r
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}
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define i64 @and_0xfff_shl_33(i64 %x) {
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; RV32I-LABEL: and_0xfff_shl_33:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a1, a0, 19
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_0xfff_shl_33:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 19
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; RV64I-NEXT: ret
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%a = and i64 %x, 4095
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%s = shl i64 %a, 33
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ret i64 %s
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}
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