derek.holloway
7502bf64a4
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179 lines
5.5 KiB
LLVM
179 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -block-placement-predecessor-limit=10 < %s \
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; RUN: | FileCheck -check-prefix=RV32I-MBPLIMIT %s
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define void @foo(i32 %a, ptr %b, i1 %c) nounwind {
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; RV32I-LABEL: foo:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: beq a3, a0, .LBB0_14
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; RV32I-NEXT: # %bb.1: # %test2
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bne a3, a0, .LBB0_14
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; RV32I-NEXT: # %bb.2: # %test3
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: blt a3, a0, .LBB0_14
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; RV32I-NEXT: # %bb.3: # %test4
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bge a3, a0, .LBB0_14
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; RV32I-NEXT: # %bb.4: # %test5
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bltu a3, a0, .LBB0_14
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; RV32I-NEXT: # %bb.5: # %test6
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bgeu a3, a0, .LBB0_14
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; RV32I-NEXT: # %bb.6: # %test7
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: blt a0, a3, .LBB0_14
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; RV32I-NEXT: # %bb.7: # %test8
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bge a0, a3, .LBB0_14
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; RV32I-NEXT: # %bb.8: # %test9
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bltu a0, a3, .LBB0_14
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; RV32I-NEXT: # %bb.9: # %test10
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bgeu a0, a3, .LBB0_14
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; RV32I-NEXT: # %bb.10: # %test11
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; RV32I-NEXT: lw zero, 0(a1)
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; RV32I-NEXT: andi a2, a2, 1
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; RV32I-NEXT: bnez a2, .LBB0_14
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; RV32I-NEXT: # %bb.11: # %test12
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: bgez a0, .LBB0_14
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; RV32I-NEXT: # %bb.12: # %test13
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: blez a0, .LBB0_14
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; RV32I-NEXT: # %bb.13: # %test14
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; RV32I-NEXT: lw zero, 0(a1)
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; RV32I-NEXT: .LBB0_14: # %end
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; RV32I-NEXT: ret
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;
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; RV32I-MBPLIMIT-LABEL: foo:
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; RV32I-MBPLIMIT: # %bb.0:
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bne a3, a0, .LBB0_2
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; RV32I-MBPLIMIT-NEXT: .LBB0_1: # %end
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; RV32I-MBPLIMIT-NEXT: ret
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; RV32I-MBPLIMIT-NEXT: .LBB0_2: # %test2
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bne a3, a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.3: # %test3
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: blt a3, a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.4: # %test4
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bge a3, a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.5: # %test5
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bltu a3, a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.6: # %test6
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bgeu a3, a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.7: # %test7
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: blt a0, a3, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.8: # %test8
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bge a0, a3, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.9: # %test9
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bltu a0, a3, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.10: # %test10
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; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bgeu a0, a3, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.11: # %test11
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; RV32I-MBPLIMIT-NEXT: lw zero, 0(a1)
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; RV32I-MBPLIMIT-NEXT: andi a2, a2, 1
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; RV32I-MBPLIMIT-NEXT: bnez a2, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.12: # %test12
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; RV32I-MBPLIMIT-NEXT: lw a0, 0(a1)
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; RV32I-MBPLIMIT-NEXT: bgez a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.13: # %test13
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; RV32I-MBPLIMIT-NEXT: lw a0, 0(a1)
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; RV32I-MBPLIMIT-NEXT: blez a0, .LBB0_1
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; RV32I-MBPLIMIT-NEXT: # %bb.14: # %test14
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; RV32I-MBPLIMIT-NEXT: lw zero, 0(a1)
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; RV32I-MBPLIMIT-NEXT: ret
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%val1 = load volatile i32, ptr %b
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%tst1 = icmp eq i32 %val1, %a
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br i1 %tst1, label %end, label %test2
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test2:
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%val2 = load volatile i32, ptr %b
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%tst2 = icmp ne i32 %val2, %a
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br i1 %tst2, label %end, label %test3
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test3:
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%val3 = load volatile i32, ptr %b
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%tst3 = icmp slt i32 %val3, %a
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br i1 %tst3, label %end, label %test4
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test4:
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%val4 = load volatile i32, ptr %b
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%tst4 = icmp sge i32 %val4, %a
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br i1 %tst4, label %end, label %test5
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test5:
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%val5 = load volatile i32, ptr %b
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%tst5 = icmp ult i32 %val5, %a
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br i1 %tst5, label %end, label %test6
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test6:
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%val6 = load volatile i32, ptr %b
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%tst6 = icmp uge i32 %val6, %a
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br i1 %tst6, label %end, label %test7
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; Check for condition codes that don't have a matching instruction
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test7:
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%val7 = load volatile i32, ptr %b
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%tst7 = icmp sgt i32 %val7, %a
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br i1 %tst7, label %end, label %test8
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test8:
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%val8 = load volatile i32, ptr %b
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%tst8 = icmp sle i32 %val8, %a
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br i1 %tst8, label %end, label %test9
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test9:
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%val9 = load volatile i32, ptr %b
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%tst9 = icmp ugt i32 %val9, %a
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br i1 %tst9, label %end, label %test10
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test10:
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%val10 = load volatile i32, ptr %b
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%tst10 = icmp ule i32 %val10, %a
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br i1 %tst10, label %end, label %test11
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; Check the case of a branch where the condition was generated in another
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; function
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test11:
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%val11 = load volatile i32, ptr %b
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br i1 %c, label %end, label %test12
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; Check that we use bgez for X > -1 which is the canonical form.
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test12:
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%val12 = load volatile i32, ptr %b
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%tst12 = icmp sgt i32 %val12, -1
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br i1 %tst12, label %end, label %test13
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; Check that we use blez (X <= 0) for (X < 1)
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test13:
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%val13 = load volatile i32, ptr %b
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%tst13 = icmp slt i32 %val13, 1
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br i1 %tst13, label %end, label %test14
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test14:
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%val14 = load volatile i32, ptr %b
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br label %end
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end:
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ret void
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}
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