derek.holloway
7502bf64a4
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241 lines
7.9 KiB
LLVM
241 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -code-model=large -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I-LARGE %s
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; This file contains tests similar to calls.ll but with cf-protection-branch
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; module flag enabled. It tests landing pad generation and NonX7 variants for
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; indirect calls.
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declare i32 @external_function(i32)
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define i32 @test_call_external(i32 %a) nounwind {
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; RV32I-LABEL: test_call_external:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lpad 0
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call external_function
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_call_external:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lpad 0
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call external_function
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64I-LARGE-LABEL: test_call_external:
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; RV64I-LARGE: # %bb.0:
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; RV64I-LARGE-NEXT: lpad 0
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; RV64I-LARGE-NEXT: addi sp, sp, -16
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; RV64I-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LARGE-NEXT: .Lpcrel_hi0:
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; RV64I-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
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; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi0)(a1)
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; RV64I-LARGE-NEXT: jalr t2
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; RV64I-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LARGE-NEXT: addi sp, sp, 16
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; RV64I-LARGE-NEXT: ret
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%1 = call i32 @external_function(i32 %a)
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ret i32 %1
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}
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define i32 @test_call_indirect(ptr %a, i32 %b) nounwind {
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; RV32I-LABEL: test_call_indirect:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lpad 0
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_call_indirect:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lpad 0
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: jalr a2
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64I-LARGE-LABEL: test_call_indirect:
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; RV64I-LARGE: # %bb.0:
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; RV64I-LARGE-NEXT: lpad 0
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; RV64I-LARGE-NEXT: addi sp, sp, -16
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; RV64I-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LARGE-NEXT: mv a2, a0
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; RV64I-LARGE-NEXT: mv a0, a1
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; RV64I-LARGE-NEXT: jalr a2
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; RV64I-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LARGE-NEXT: addi sp, sp, 16
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; RV64I-LARGE-NEXT: ret
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%1 = call i32 %a(i32 %b)
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ret i32 %1
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}
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; Make sure we don't use t0 as the source for jalr as that is a hint to pop the
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; return address stack on some microarchitectures.
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define i32 @test_call_indirect_no_t0(ptr %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) nounwind {
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; RV32I-LABEL: test_call_indirect_no_t0:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lpad 0
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv t1, a0
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: mv a1, a2
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; RV32I-NEXT: mv a2, a3
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; RV32I-NEXT: mv a3, a4
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; RV32I-NEXT: mv a4, a5
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; RV32I-NEXT: mv a5, a6
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; RV32I-NEXT: mv a6, a7
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; RV32I-NEXT: jalr t1
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_call_indirect_no_t0:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lpad 0
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv t1, a0
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: mv a1, a2
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; RV64I-NEXT: mv a2, a3
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; RV64I-NEXT: mv a3, a4
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; RV64I-NEXT: mv a4, a5
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; RV64I-NEXT: mv a5, a6
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; RV64I-NEXT: mv a6, a7
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; RV64I-NEXT: jalr t1
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64I-LARGE-LABEL: test_call_indirect_no_t0:
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; RV64I-LARGE: # %bb.0:
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; RV64I-LARGE-NEXT: lpad 0
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; RV64I-LARGE-NEXT: addi sp, sp, -16
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; RV64I-LARGE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-LARGE-NEXT: mv t1, a0
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; RV64I-LARGE-NEXT: mv a0, a1
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; RV64I-LARGE-NEXT: mv a1, a2
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; RV64I-LARGE-NEXT: mv a2, a3
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; RV64I-LARGE-NEXT: mv a3, a4
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; RV64I-LARGE-NEXT: mv a4, a5
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; RV64I-LARGE-NEXT: mv a5, a6
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; RV64I-LARGE-NEXT: mv a6, a7
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; RV64I-LARGE-NEXT: jalr t1
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; RV64I-LARGE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-LARGE-NEXT: addi sp, sp, 16
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; RV64I-LARGE-NEXT: ret
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%1 = call i32 %a(i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h)
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ret i32 %1
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}
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declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
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define fastcc void @fastcc_call_nonfastcc(){
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; RV32I-LABEL: fastcc_call_nonfastcc:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lpad 0
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: .cfi_def_cfa_offset 16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: .cfi_offset ra, -4
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; RV32I-NEXT: li t0, 10
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; RV32I-NEXT: li t1, 9
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: li a1, 2
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; RV32I-NEXT: li a2, 3
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; RV32I-NEXT: li a3, 4
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; RV32I-NEXT: li a4, 5
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; RV32I-NEXT: li a5, 6
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; RV32I-NEXT: li a6, 7
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; RV32I-NEXT: li a7, 8
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; RV32I-NEXT: sw t1, 0(sp)
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; RV32I-NEXT: sw t0, 4(sp)
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; RV32I-NEXT: call external_many_args
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: .cfi_restore ra
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fastcc_call_nonfastcc:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lpad 0
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; RV64I-NEXT: addi sp, sp, -32
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; RV64I-NEXT: .cfi_def_cfa_offset 32
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; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-NEXT: .cfi_offset ra, -8
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; RV64I-NEXT: li t0, 10
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; RV64I-NEXT: li t1, 9
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: li a1, 2
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; RV64I-NEXT: li a2, 3
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; RV64I-NEXT: li a3, 4
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; RV64I-NEXT: li a4, 5
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; RV64I-NEXT: li a5, 6
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; RV64I-NEXT: li a6, 7
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; RV64I-NEXT: li a7, 8
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; RV64I-NEXT: sd t1, 0(sp)
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; RV64I-NEXT: sd t0, 8(sp)
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; RV64I-NEXT: call external_many_args
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; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64I-NEXT: .cfi_restore ra
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; RV64I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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;
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; RV64I-LARGE-LABEL: fastcc_call_nonfastcc:
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; RV64I-LARGE: # %bb.0:
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; RV64I-LARGE-NEXT: lpad 0
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; RV64I-LARGE-NEXT: addi sp, sp, -32
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; RV64I-LARGE-NEXT: .cfi_def_cfa_offset 32
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; RV64I-LARGE-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-LARGE-NEXT: .cfi_offset ra, -8
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; RV64I-LARGE-NEXT: li t0, 10
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; RV64I-LARGE-NEXT: li t1, 9
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; RV64I-LARGE-NEXT: .Lpcrel_hi1:
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; RV64I-LARGE-NEXT: auipc a5, %pcrel_hi(.LCPI3_0)
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; RV64I-LARGE-NEXT: li a0, 1
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; RV64I-LARGE-NEXT: li a1, 2
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; RV64I-LARGE-NEXT: li a2, 3
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; RV64I-LARGE-NEXT: li a3, 4
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; RV64I-LARGE-NEXT: li a4, 5
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; RV64I-LARGE-NEXT: ld t2, %pcrel_lo(.Lpcrel_hi1)(a5)
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; RV64I-LARGE-NEXT: li a5, 6
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; RV64I-LARGE-NEXT: li a6, 7
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; RV64I-LARGE-NEXT: li a7, 8
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; RV64I-LARGE-NEXT: sd t1, 0(sp)
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; RV64I-LARGE-NEXT: sd t0, 8(sp)
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; RV64I-LARGE-NEXT: jalr t2
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; RV64I-LARGE-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64I-LARGE-NEXT: .cfi_restore ra
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; RV64I-LARGE-NEXT: addi sp, sp, 32
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; RV64I-LARGE-NEXT: .cfi_def_cfa_offset 0
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; RV64I-LARGE-NEXT: ret
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call void @external_many_args(i32 1, i32 2,i32 3,i32 4,i32 5,i32 6,i32 7,i32 8,i32 9,i32 10)
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ret void
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}
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!llvm.module.flags = !{!0}
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!0 = !{i32 8, !"cf-protection-branch", i32 1}
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