derek.holloway
7502bf64a4
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973 lines
28 KiB
LLVM
973 lines
28 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32,RV32IM %s
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; RUN: llc -mtriple=riscv32 -mattr=+m,+zba,+zbb \
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; RUN: -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32,RV32IMZB %s
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64,RV64IM %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb \
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; RUN: -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64,RV64IMZB %s
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; Test that there is a single shift after the mul and no addition.
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define i32 @udiv_constant_no_add(i32 %a) nounwind {
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; RV32-LABEL: udiv_constant_no_add:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a1, 838861
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; RV32-NEXT: addi a1, a1, -819
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; RV32-NEXT: mulhu a0, a0, a1
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; RV32-NEXT: srli a0, a0, 2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: udiv_constant_no_add:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 32
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; RV64-NEXT: lui a1, 838861
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; RV64-NEXT: addi a1, a1, -819
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; RV64-NEXT: slli a1, a1, 32
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; RV64-NEXT: mulhu a0, a0, a1
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; RV64-NEXT: srli a0, a0, 34
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; RV64-NEXT: ret
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%1 = udiv i32 %a, 5
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ret i32 %1
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}
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; This constant requires a sub, shrli, add sequence after the mul.
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define i32 @udiv_constant_add(i32 %a) nounwind {
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; RV32-LABEL: udiv_constant_add:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a1, 149797
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; RV32-NEXT: addi a1, a1, -1755
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: srli a0, a0, 1
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: srli a0, a0, 2
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; RV32-NEXT: ret
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;
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; RV64IM-LABEL: udiv_constant_add:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a0, a0, 32
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; RV64IM-NEXT: lui a1, 293
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; RV64IM-NEXT: srli a0, a0, 32
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; RV64IM-NEXT: addi a1, a1, -1755
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -1755
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; RV64IM-NEXT: slli a1, a1, 29
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; RV64IM-NEXT: mulhu a0, a0, a1
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; RV64IM-NEXT: ret
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;
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; RV64IMZB-LABEL: udiv_constant_add:
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; RV64IMZB: # %bb.0:
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; RV64IMZB-NEXT: zext.w a0, a0
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; RV64IMZB-NEXT: lui a1, 293
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; RV64IMZB-NEXT: addi a1, a1, -1755
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; RV64IMZB-NEXT: slli a1, a1, 12
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; RV64IMZB-NEXT: addi a1, a1, -1755
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; RV64IMZB-NEXT: slli a1, a1, 29
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; RV64IMZB-NEXT: mulhu a0, a0, a1
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; RV64IMZB-NEXT: ret
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%1 = udiv i32 %a, 7
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ret i32 %1
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}
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define i64 @udiv64_constant_no_add(i64 %a) nounwind {
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; RV32-LABEL: udiv64_constant_no_add:
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; RV32: # %bb.0:
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; RV32-NEXT: add a2, a0, a1
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; RV32-NEXT: lui a3, 838861
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; RV32-NEXT: sltu a4, a2, a0
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; RV32-NEXT: addi a5, a3, -819
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; RV32-NEXT: addi a3, a3, -820
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; RV32-NEXT: add a2, a2, a4
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; RV32-NEXT: mulhu a4, a2, a5
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; RV32-NEXT: srli a6, a4, 2
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; RV32-NEXT: andi a4, a4, -4
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; RV32-NEXT: add a4, a4, a6
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; RV32-NEXT: sub a2, a2, a4
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; RV32-NEXT: sub a4, a0, a2
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; RV32-NEXT: sltu a0, a0, a2
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; RV32-NEXT: mul a2, a4, a3
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; RV32-NEXT: mulhu a3, a4, a5
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; RV32-NEXT: sub a1, a1, a0
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; RV32-NEXT: add a2, a3, a2
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; RV32-NEXT: mul a1, a1, a5
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; RV32-NEXT: add a1, a2, a1
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; RV32-NEXT: mul a0, a4, a5
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; RV32-NEXT: ret
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;
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; RV64-LABEL: udiv64_constant_no_add:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 838861
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; RV64-NEXT: addi a1, a1, -819
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; RV64-NEXT: slli a2, a1, 32
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: mulhu a0, a0, a1
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; RV64-NEXT: srli a0, a0, 2
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; RV64-NEXT: ret
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%1 = udiv i64 %a, 5
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ret i64 %1
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}
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define i64 @udiv64_constant_add(i64 %a) nounwind {
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; RV32IM-LABEL: udiv64_constant_add:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a2, 262144
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; RV32IM-NEXT: slli a3, a1, 2
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; RV32IM-NEXT: srli a4, a0, 30
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; RV32IM-NEXT: srli a5, a1, 28
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; RV32IM-NEXT: lui a6, 149797
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; RV32IM-NEXT: or a3, a4, a3
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; RV32IM-NEXT: lui a4, 449390
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; RV32IM-NEXT: addi a2, a2, -1
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; RV32IM-NEXT: and a3, a3, a2
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; RV32IM-NEXT: and a2, a0, a2
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; RV32IM-NEXT: add a2, a2, a3
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; RV32IM-NEXT: lui a3, 748983
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; RV32IM-NEXT: addi a6, a6, -1755
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; RV32IM-NEXT: addi a4, a4, -1171
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; RV32IM-NEXT: addi a3, a3, -585
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; RV32IM-NEXT: add a2, a2, a5
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; RV32IM-NEXT: mulhu a5, a2, a6
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; RV32IM-NEXT: sub a6, a2, a5
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; RV32IM-NEXT: srli a6, a6, 1
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; RV32IM-NEXT: add a5, a6, a5
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; RV32IM-NEXT: srli a5, a5, 2
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; RV32IM-NEXT: slli a6, a5, 3
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; RV32IM-NEXT: sub a5, a5, a6
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; RV32IM-NEXT: add a2, a2, a5
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; RV32IM-NEXT: sub a5, a0, a2
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; RV32IM-NEXT: sltu a0, a0, a2
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; RV32IM-NEXT: mul a2, a5, a4
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; RV32IM-NEXT: mulhu a4, a5, a3
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; RV32IM-NEXT: sub a1, a1, a0
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; RV32IM-NEXT: add a2, a4, a2
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; RV32IM-NEXT: mul a1, a1, a3
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; RV32IM-NEXT: add a1, a2, a1
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; RV32IM-NEXT: mul a0, a5, a3
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; RV32IM-NEXT: ret
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;
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; RV32IMZB-LABEL: udiv64_constant_add:
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; RV32IMZB: # %bb.0:
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; RV32IMZB-NEXT: srli a2, a0, 30
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; RV32IMZB-NEXT: lui a3, 786432
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; RV32IMZB-NEXT: slli a4, a0, 2
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; RV32IMZB-NEXT: srli a5, a1, 28
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; RV32IMZB-NEXT: lui a6, 149797
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; RV32IMZB-NEXT: sh2add a2, a1, a2
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; RV32IMZB-NEXT: andn a2, a2, a3
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; RV32IMZB-NEXT: lui a3, 449390
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; RV32IMZB-NEXT: srli a4, a4, 2
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; RV32IMZB-NEXT: add a4, a4, a5
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; RV32IMZB-NEXT: lui a5, 748983
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; RV32IMZB-NEXT: addi a6, a6, -1755
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; RV32IMZB-NEXT: addi a3, a3, -1171
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; RV32IMZB-NEXT: addi a5, a5, -585
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; RV32IMZB-NEXT: add a2, a4, a2
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; RV32IMZB-NEXT: mulhu a4, a2, a6
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; RV32IMZB-NEXT: sub a6, a2, a4
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; RV32IMZB-NEXT: srli a6, a6, 1
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; RV32IMZB-NEXT: add a4, a6, a4
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; RV32IMZB-NEXT: srli a4, a4, 2
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; RV32IMZB-NEXT: slli a6, a4, 3
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; RV32IMZB-NEXT: sub a4, a4, a6
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; RV32IMZB-NEXT: add a2, a2, a4
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; RV32IMZB-NEXT: sub a4, a0, a2
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; RV32IMZB-NEXT: sltu a0, a0, a2
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; RV32IMZB-NEXT: mul a2, a4, a3
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; RV32IMZB-NEXT: mulhu a3, a4, a5
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; RV32IMZB-NEXT: sub a1, a1, a0
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; RV32IMZB-NEXT: add a2, a3, a2
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; RV32IMZB-NEXT: mul a1, a1, a5
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; RV32IMZB-NEXT: add a1, a2, a1
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; RV32IMZB-NEXT: mul a0, a4, a5
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; RV32IMZB-NEXT: ret
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;
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; RV64-LABEL: udiv64_constant_add:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, %hi(.LCPI3_0)
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; RV64-NEXT: ld a1, %lo(.LCPI3_0)(a1)
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: srli a0, a0, 1
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: srli a0, a0, 2
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; RV64-NEXT: ret
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%1 = udiv i64 %a, 7
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ret i64 %1
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}
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define i8 @udiv8_constant_no_add(i8 %a) nounwind {
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; RV32-LABEL: udiv8_constant_no_add:
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; RV32: # %bb.0:
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; RV32-NEXT: zext.b a0, a0
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; RV32-NEXT: li a1, 205
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; RV32-NEXT: mul a0, a0, a1
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; RV32-NEXT: srli a0, a0, 10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: udiv8_constant_no_add:
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; RV64: # %bb.0:
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; RV64-NEXT: zext.b a0, a0
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; RV64-NEXT: li a1, 205
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; RV64-NEXT: mul a0, a0, a1
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; RV64-NEXT: srli a0, a0, 10
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; RV64-NEXT: ret
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%1 = udiv i8 %a, 5
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ret i8 %1
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}
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define i8 @udiv8_constant_add(i8 %a) nounwind {
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; RV32IM-LABEL: udiv8_constant_add:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: zext.b a1, a0
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; RV32IM-NEXT: li a2, 37
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: srli a1, a1, 8
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; RV32IM-NEXT: sub a0, a0, a1
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; RV32IM-NEXT: slli a0, a0, 24
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; RV32IM-NEXT: srli a0, a0, 25
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: srli a0, a0, 2
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; RV32IM-NEXT: ret
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;
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; RV32IMZB-LABEL: udiv8_constant_add:
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; RV32IMZB: # %bb.0:
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; RV32IMZB-NEXT: zext.b a1, a0
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; RV32IMZB-NEXT: sh3add a2, a1, a1
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; RV32IMZB-NEXT: sh2add a1, a2, a1
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; RV32IMZB-NEXT: srli a1, a1, 8
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; RV32IMZB-NEXT: sub a0, a0, a1
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; RV32IMZB-NEXT: slli a0, a0, 24
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; RV32IMZB-NEXT: srli a0, a0, 25
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; RV32IMZB-NEXT: add a0, a0, a1
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; RV32IMZB-NEXT: srli a0, a0, 2
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; RV32IMZB-NEXT: ret
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;
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; RV64IM-LABEL: udiv8_constant_add:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: zext.b a1, a0
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; RV64IM-NEXT: li a2, 37
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; RV64IM-NEXT: mul a1, a1, a2
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; RV64IM-NEXT: srli a1, a1, 8
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; RV64IM-NEXT: sub a0, a0, a1
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; RV64IM-NEXT: slli a0, a0, 56
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; RV64IM-NEXT: srli a0, a0, 57
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; RV64IM-NEXT: add a0, a0, a1
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; RV64IM-NEXT: srli a0, a0, 2
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; RV64IM-NEXT: ret
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;
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; RV64IMZB-LABEL: udiv8_constant_add:
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; RV64IMZB: # %bb.0:
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; RV64IMZB-NEXT: zext.b a1, a0
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; RV64IMZB-NEXT: sh3add a2, a1, a1
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; RV64IMZB-NEXT: sh2add a1, a2, a1
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; RV64IMZB-NEXT: srli a1, a1, 8
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; RV64IMZB-NEXT: sub a0, a0, a1
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; RV64IMZB-NEXT: slli a0, a0, 56
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; RV64IMZB-NEXT: srli a0, a0, 57
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; RV64IMZB-NEXT: add a0, a0, a1
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; RV64IMZB-NEXT: srli a0, a0, 2
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; RV64IMZB-NEXT: ret
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%1 = udiv i8 %a, 7
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ret i8 %1
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}
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define i16 @udiv16_constant_no_add(i16 %a) nounwind {
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; RV32-LABEL: udiv16_constant_no_add:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 16
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; RV32-NEXT: lui a1, 838864
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; RV32-NEXT: mulhu a0, a0, a1
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; RV32-NEXT: srli a0, a0, 18
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; RV32-NEXT: ret
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;
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; RV64-LABEL: udiv16_constant_no_add:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 52429
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; RV64-NEXT: slli a1, a1, 4
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; RV64-NEXT: slli a0, a0, 48
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; RV64-NEXT: mulhu a0, a0, a1
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; RV64-NEXT: srli a0, a0, 18
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; RV64-NEXT: ret
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%1 = udiv i16 %a, 5
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ret i16 %1
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}
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|
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define i16 @udiv16_constant_add(i16 %a) nounwind {
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|
; RV32-LABEL: udiv16_constant_add:
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; RV32: # %bb.0:
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|
; RV32-NEXT: slli a1, a0, 16
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|
; RV32-NEXT: lui a2, 149808
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|
; RV32-NEXT: mulhu a1, a1, a2
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|
; RV32-NEXT: srli a1, a1, 16
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|
; RV32-NEXT: sub a0, a0, a1
|
|
; RV32-NEXT: slli a0, a0, 16
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|
; RV32-NEXT: srli a0, a0, 17
|
|
; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: srli a0, a0, 2
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; RV32-NEXT: ret
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;
|
|
; RV64-LABEL: udiv16_constant_add:
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|
; RV64: # %bb.0:
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|
; RV64-NEXT: slli a1, a0, 48
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|
; RV64-NEXT: lui a2, 149808
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|
; RV64-NEXT: mulhu a1, a1, a2
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; RV64-NEXT: srli a1, a1, 16
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: slli a0, a0, 48
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|
; RV64-NEXT: srli a0, a0, 49
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|
; RV64-NEXT: add a0, a0, a1
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|
; RV64-NEXT: srli a0, a0, 2
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|
; RV64-NEXT: ret
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|
%1 = udiv i16 %a, 7
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|
ret i16 %1
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}
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|
|
; Test the simplest case a srli and an add after the mul. No srai.
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define i32 @sdiv_constant_no_srai(i32 %a) nounwind {
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|
; RV32-LABEL: sdiv_constant_no_srai:
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|
; RV32: # %bb.0:
|
|
; RV32-NEXT: lui a1, 349525
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|
; RV32-NEXT: addi a1, a1, 1366
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|
; RV32-NEXT: mulh a0, a0, a1
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|
; RV32-NEXT: srli a1, a0, 31
|
|
; RV32-NEXT: add a0, a0, a1
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv_constant_no_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: sext.w a0, a0
|
|
; RV64-NEXT: lui a1, 349525
|
|
; RV64-NEXT: addi a1, a1, 1366
|
|
; RV64-NEXT: mul a0, a0, a1
|
|
; RV64-NEXT: srli a1, a0, 63
|
|
; RV64-NEXT: srli a0, a0, 32
|
|
; RV64-NEXT: addw a0, a0, a1
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i32 %a, 3
|
|
ret i32 %1
|
|
}
|
|
|
|
; This constant requires an srai between the mul and the add.
|
|
define i32 @sdiv_constant_srai(i32 %a) nounwind {
|
|
; RV32-LABEL: sdiv_constant_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: lui a1, 419430
|
|
; RV32-NEXT: addi a1, a1, 1639
|
|
; RV32-NEXT: mulh a0, a0, a1
|
|
; RV32-NEXT: srli a1, a0, 31
|
|
; RV32-NEXT: srai a0, a0, 1
|
|
; RV32-NEXT: add a0, a0, a1
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv_constant_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: sext.w a0, a0
|
|
; RV64-NEXT: lui a1, 419430
|
|
; RV64-NEXT: addi a1, a1, 1639
|
|
; RV64-NEXT: mul a0, a0, a1
|
|
; RV64-NEXT: srli a1, a0, 63
|
|
; RV64-NEXT: srai a0, a0, 33
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i32 %a, 5
|
|
ret i32 %1
|
|
}
|
|
|
|
; This constant requires an add and an srai after the mul.
|
|
define i32 @sdiv_constant_add_srai(i32 %a) nounwind {
|
|
; RV32-LABEL: sdiv_constant_add_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: lui a1, 599186
|
|
; RV32-NEXT: addi a1, a1, 1171
|
|
; RV32-NEXT: mulh a1, a0, a1
|
|
; RV32-NEXT: add a0, a1, a0
|
|
; RV32-NEXT: srli a1, a0, 31
|
|
; RV32-NEXT: srai a0, a0, 2
|
|
; RV32-NEXT: add a0, a0, a1
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv_constant_add_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: sext.w a1, a0
|
|
; RV64-NEXT: lui a2, 599186
|
|
; RV64-NEXT: addi a2, a2, 1171
|
|
; RV64-NEXT: mul a1, a1, a2
|
|
; RV64-NEXT: srli a1, a1, 32
|
|
; RV64-NEXT: add a0, a1, a0
|
|
; RV64-NEXT: srliw a1, a0, 31
|
|
; RV64-NEXT: sraiw a0, a0, 2
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i32 %a, 7
|
|
ret i32 %1
|
|
}
|
|
|
|
; This constant requires a sub and an srai after the mul.
|
|
define i32 @sdiv_constant_sub_srai(i32 %a) nounwind {
|
|
; RV32-LABEL: sdiv_constant_sub_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: lui a1, 449390
|
|
; RV32-NEXT: addi a1, a1, -1171
|
|
; RV32-NEXT: mulh a1, a0, a1
|
|
; RV32-NEXT: sub a1, a1, a0
|
|
; RV32-NEXT: srli a0, a1, 31
|
|
; RV32-NEXT: srai a1, a1, 2
|
|
; RV32-NEXT: add a0, a1, a0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv_constant_sub_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: sext.w a1, a0
|
|
; RV64-NEXT: lui a2, 449390
|
|
; RV64-NEXT: addi a2, a2, -1171
|
|
; RV64-NEXT: mul a1, a1, a2
|
|
; RV64-NEXT: srli a1, a1, 32
|
|
; RV64-NEXT: sub a1, a1, a0
|
|
; RV64-NEXT: srliw a0, a1, 31
|
|
; RV64-NEXT: sraiw a1, a1, 2
|
|
; RV64-NEXT: add a0, a1, a0
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i32 %a, -7
|
|
ret i32 %1
|
|
}
|
|
|
|
define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {
|
|
; RV32-LABEL: sdiv64_constant_no_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: li a2, 3
|
|
; RV32-NEXT: li a3, 0
|
|
; RV32-NEXT: call __divdi3
|
|
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv64_constant_no_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a1, %hi(.LCPI12_0)
|
|
; RV64-NEXT: ld a1, %lo(.LCPI12_0)(a1)
|
|
; RV64-NEXT: mulh a0, a0, a1
|
|
; RV64-NEXT: srli a1, a0, 63
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i64 %a, 3
|
|
ret i64 %1
|
|
}
|
|
|
|
define i64 @sdiv64_constant_srai(i64 %a) nounwind {
|
|
; RV32-LABEL: sdiv64_constant_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: li a2, 5
|
|
; RV32-NEXT: li a3, 0
|
|
; RV32-NEXT: call __divdi3
|
|
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv64_constant_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a1, %hi(.LCPI13_0)
|
|
; RV64-NEXT: ld a1, %lo(.LCPI13_0)(a1)
|
|
; RV64-NEXT: mulh a0, a0, a1
|
|
; RV64-NEXT: srli a1, a0, 63
|
|
; RV64-NEXT: srai a0, a0, 1
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i64 %a, 5
|
|
ret i64 %1
|
|
}
|
|
|
|
define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {
|
|
; RV32-LABEL: sdiv64_constant_add_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: li a2, 15
|
|
; RV32-NEXT: li a3, 0
|
|
; RV32-NEXT: call __divdi3
|
|
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv64_constant_add_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a1, 559241
|
|
; RV64-NEXT: addi a1, a1, -1911
|
|
; RV64-NEXT: slli a2, a1, 32
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: mulh a1, a0, a1
|
|
; RV64-NEXT: add a0, a1, a0
|
|
; RV64-NEXT: srli a1, a0, 63
|
|
; RV64-NEXT: srai a0, a0, 3
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i64 %a, 15
|
|
ret i64 %1
|
|
}
|
|
|
|
define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {
|
|
; RV32-LABEL: sdiv64_constant_sub_srai:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -16
|
|
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: li a2, -3
|
|
; RV32-NEXT: li a3, -1
|
|
; RV32-NEXT: call __divdi3
|
|
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 16
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: sdiv64_constant_sub_srai:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a1, 349525
|
|
; RV64-NEXT: addi a1, a1, 1365
|
|
; RV64-NEXT: slli a2, a1, 32
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: mulh a1, a0, a1
|
|
; RV64-NEXT: sub a1, a1, a0
|
|
; RV64-NEXT: srli a0, a1, 63
|
|
; RV64-NEXT: srai a1, a1, 1
|
|
; RV64-NEXT: add a0, a1, a0
|
|
; RV64-NEXT: ret
|
|
%1 = sdiv i64 %a, -3
|
|
ret i64 %1
|
|
}
|
|
|
|
define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv8_constant_no_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a0, a0, 24
|
|
; RV32IM-NEXT: li a1, 86
|
|
; RV32IM-NEXT: srai a0, a0, 24
|
|
; RV32IM-NEXT: mul a0, a0, a1
|
|
; RV32IM-NEXT: srli a1, a0, 31
|
|
; RV32IM-NEXT: srli a0, a0, 8
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv8_constant_no_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.b a0, a0
|
|
; RV32IMZB-NEXT: li a1, 86
|
|
; RV32IMZB-NEXT: mul a0, a0, a1
|
|
; RV32IMZB-NEXT: srli a1, a0, 31
|
|
; RV32IMZB-NEXT: srli a0, a0, 8
|
|
; RV32IMZB-NEXT: add a0, a0, a1
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv8_constant_no_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a0, a0, 56
|
|
; RV64IM-NEXT: li a1, 86
|
|
; RV64IM-NEXT: srai a0, a0, 56
|
|
; RV64IM-NEXT: mul a0, a0, a1
|
|
; RV64IM-NEXT: srli a1, a0, 63
|
|
; RV64IM-NEXT: srli a0, a0, 8
|
|
; RV64IM-NEXT: add a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv8_constant_no_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.b a0, a0
|
|
; RV64IMZB-NEXT: li a1, 86
|
|
; RV64IMZB-NEXT: mul a0, a0, a1
|
|
; RV64IMZB-NEXT: srli a1, a0, 63
|
|
; RV64IMZB-NEXT: srli a0, a0, 8
|
|
; RV64IMZB-NEXT: add a0, a0, a1
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i8 %a, 3
|
|
ret i8 %1
|
|
}
|
|
|
|
define i8 @sdiv8_constant_srai(i8 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv8_constant_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a0, a0, 24
|
|
; RV32IM-NEXT: li a1, 103
|
|
; RV32IM-NEXT: srai a0, a0, 24
|
|
; RV32IM-NEXT: mul a0, a0, a1
|
|
; RV32IM-NEXT: srli a1, a0, 31
|
|
; RV32IM-NEXT: srai a0, a0, 9
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv8_constant_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.b a0, a0
|
|
; RV32IMZB-NEXT: li a1, 103
|
|
; RV32IMZB-NEXT: mul a0, a0, a1
|
|
; RV32IMZB-NEXT: srli a1, a0, 31
|
|
; RV32IMZB-NEXT: srai a0, a0, 9
|
|
; RV32IMZB-NEXT: add a0, a0, a1
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv8_constant_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a0, a0, 56
|
|
; RV64IM-NEXT: li a1, 103
|
|
; RV64IM-NEXT: srai a0, a0, 56
|
|
; RV64IM-NEXT: mul a0, a0, a1
|
|
; RV64IM-NEXT: srli a1, a0, 63
|
|
; RV64IM-NEXT: srai a0, a0, 9
|
|
; RV64IM-NEXT: add a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv8_constant_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.b a0, a0
|
|
; RV64IMZB-NEXT: li a1, 103
|
|
; RV64IMZB-NEXT: mul a0, a0, a1
|
|
; RV64IMZB-NEXT: srli a1, a0, 63
|
|
; RV64IMZB-NEXT: srai a0, a0, 9
|
|
; RV64IMZB-NEXT: add a0, a0, a1
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i8 %a, 5
|
|
ret i8 %1
|
|
}
|
|
|
|
define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv8_constant_add_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a1, a0, 24
|
|
; RV32IM-NEXT: li a2, -109
|
|
; RV32IM-NEXT: srai a1, a1, 24
|
|
; RV32IM-NEXT: mul a1, a1, a2
|
|
; RV32IM-NEXT: srli a1, a1, 8
|
|
; RV32IM-NEXT: add a0, a1, a0
|
|
; RV32IM-NEXT: slli a0, a0, 24
|
|
; RV32IM-NEXT: srli a1, a0, 31
|
|
; RV32IM-NEXT: srai a0, a0, 26
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv8_constant_add_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.b a1, a0
|
|
; RV32IMZB-NEXT: li a2, -109
|
|
; RV32IMZB-NEXT: mul a1, a1, a2
|
|
; RV32IMZB-NEXT: srli a1, a1, 8
|
|
; RV32IMZB-NEXT: add a0, a1, a0
|
|
; RV32IMZB-NEXT: slli a0, a0, 24
|
|
; RV32IMZB-NEXT: srli a1, a0, 31
|
|
; RV32IMZB-NEXT: srai a0, a0, 26
|
|
; RV32IMZB-NEXT: add a0, a0, a1
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv8_constant_add_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a1, a0, 56
|
|
; RV64IM-NEXT: li a2, -109
|
|
; RV64IM-NEXT: srai a1, a1, 56
|
|
; RV64IM-NEXT: mul a1, a1, a2
|
|
; RV64IM-NEXT: srli a1, a1, 8
|
|
; RV64IM-NEXT: add a0, a1, a0
|
|
; RV64IM-NEXT: slli a0, a0, 56
|
|
; RV64IM-NEXT: srli a1, a0, 63
|
|
; RV64IM-NEXT: srai a0, a0, 58
|
|
; RV64IM-NEXT: add a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv8_constant_add_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.b a1, a0
|
|
; RV64IMZB-NEXT: li a2, -109
|
|
; RV64IMZB-NEXT: mul a1, a1, a2
|
|
; RV64IMZB-NEXT: srli a1, a1, 8
|
|
; RV64IMZB-NEXT: add a0, a1, a0
|
|
; RV64IMZB-NEXT: slli a0, a0, 56
|
|
; RV64IMZB-NEXT: srli a1, a0, 63
|
|
; RV64IMZB-NEXT: srai a0, a0, 58
|
|
; RV64IMZB-NEXT: add a0, a0, a1
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i8 %a, 7
|
|
ret i8 %1
|
|
}
|
|
|
|
define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv8_constant_sub_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a1, a0, 24
|
|
; RV32IM-NEXT: li a2, 109
|
|
; RV32IM-NEXT: srai a1, a1, 24
|
|
; RV32IM-NEXT: mul a1, a1, a2
|
|
; RV32IM-NEXT: srli a1, a1, 8
|
|
; RV32IM-NEXT: sub a1, a1, a0
|
|
; RV32IM-NEXT: slli a1, a1, 24
|
|
; RV32IM-NEXT: srli a0, a1, 31
|
|
; RV32IM-NEXT: srai a1, a1, 26
|
|
; RV32IM-NEXT: add a0, a1, a0
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv8_constant_sub_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.b a1, a0
|
|
; RV32IMZB-NEXT: li a2, 109
|
|
; RV32IMZB-NEXT: mul a1, a1, a2
|
|
; RV32IMZB-NEXT: srli a1, a1, 8
|
|
; RV32IMZB-NEXT: sub a1, a1, a0
|
|
; RV32IMZB-NEXT: slli a1, a1, 24
|
|
; RV32IMZB-NEXT: srli a0, a1, 31
|
|
; RV32IMZB-NEXT: srai a1, a1, 26
|
|
; RV32IMZB-NEXT: add a0, a1, a0
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv8_constant_sub_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a1, a0, 56
|
|
; RV64IM-NEXT: li a2, 109
|
|
; RV64IM-NEXT: srai a1, a1, 56
|
|
; RV64IM-NEXT: mul a1, a1, a2
|
|
; RV64IM-NEXT: srli a1, a1, 8
|
|
; RV64IM-NEXT: sub a1, a1, a0
|
|
; RV64IM-NEXT: slli a1, a1, 56
|
|
; RV64IM-NEXT: srli a0, a1, 63
|
|
; RV64IM-NEXT: srai a1, a1, 58
|
|
; RV64IM-NEXT: add a0, a1, a0
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv8_constant_sub_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.b a1, a0
|
|
; RV64IMZB-NEXT: li a2, 109
|
|
; RV64IMZB-NEXT: mul a1, a1, a2
|
|
; RV64IMZB-NEXT: srli a1, a1, 8
|
|
; RV64IMZB-NEXT: sub a1, a1, a0
|
|
; RV64IMZB-NEXT: slli a1, a1, 56
|
|
; RV64IMZB-NEXT: srli a0, a1, 63
|
|
; RV64IMZB-NEXT: srai a1, a1, 58
|
|
; RV64IMZB-NEXT: add a0, a1, a0
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i8 %a, -7
|
|
ret i8 %1
|
|
}
|
|
|
|
define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv16_constant_no_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a0, a0, 16
|
|
; RV32IM-NEXT: lui a1, 5
|
|
; RV32IM-NEXT: srai a0, a0, 16
|
|
; RV32IM-NEXT: addi a1, a1, 1366
|
|
; RV32IM-NEXT: mul a0, a0, a1
|
|
; RV32IM-NEXT: srli a1, a0, 31
|
|
; RV32IM-NEXT: srli a0, a0, 16
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv16_constant_no_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.h a0, a0
|
|
; RV32IMZB-NEXT: lui a1, 5
|
|
; RV32IMZB-NEXT: addi a1, a1, 1366
|
|
; RV32IMZB-NEXT: mul a0, a0, a1
|
|
; RV32IMZB-NEXT: srli a1, a0, 31
|
|
; RV32IMZB-NEXT: srli a0, a0, 16
|
|
; RV32IMZB-NEXT: add a0, a0, a1
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv16_constant_no_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a0, a0, 48
|
|
; RV64IM-NEXT: lui a1, 5
|
|
; RV64IM-NEXT: srai a0, a0, 48
|
|
; RV64IM-NEXT: addi a1, a1, 1366
|
|
; RV64IM-NEXT: mul a0, a0, a1
|
|
; RV64IM-NEXT: srli a1, a0, 63
|
|
; RV64IM-NEXT: srli a0, a0, 16
|
|
; RV64IM-NEXT: add a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv16_constant_no_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.h a0, a0
|
|
; RV64IMZB-NEXT: lui a1, 5
|
|
; RV64IMZB-NEXT: addi a1, a1, 1366
|
|
; RV64IMZB-NEXT: mul a0, a0, a1
|
|
; RV64IMZB-NEXT: srli a1, a0, 63
|
|
; RV64IMZB-NEXT: srli a0, a0, 16
|
|
; RV64IMZB-NEXT: add a0, a0, a1
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i16 %a, 3
|
|
ret i16 %1
|
|
}
|
|
|
|
define i16 @sdiv16_constant_srai(i16 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv16_constant_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a0, a0, 16
|
|
; RV32IM-NEXT: lui a1, 6
|
|
; RV32IM-NEXT: srai a0, a0, 16
|
|
; RV32IM-NEXT: addi a1, a1, 1639
|
|
; RV32IM-NEXT: mul a0, a0, a1
|
|
; RV32IM-NEXT: srli a1, a0, 31
|
|
; RV32IM-NEXT: srai a0, a0, 17
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv16_constant_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.h a0, a0
|
|
; RV32IMZB-NEXT: lui a1, 6
|
|
; RV32IMZB-NEXT: addi a1, a1, 1639
|
|
; RV32IMZB-NEXT: mul a0, a0, a1
|
|
; RV32IMZB-NEXT: srli a1, a0, 31
|
|
; RV32IMZB-NEXT: srai a0, a0, 17
|
|
; RV32IMZB-NEXT: add a0, a0, a1
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv16_constant_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a0, a0, 48
|
|
; RV64IM-NEXT: lui a1, 6
|
|
; RV64IM-NEXT: srai a0, a0, 48
|
|
; RV64IM-NEXT: addi a1, a1, 1639
|
|
; RV64IM-NEXT: mul a0, a0, a1
|
|
; RV64IM-NEXT: srli a1, a0, 63
|
|
; RV64IM-NEXT: srai a0, a0, 17
|
|
; RV64IM-NEXT: add a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv16_constant_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.h a0, a0
|
|
; RV64IMZB-NEXT: lui a1, 6
|
|
; RV64IMZB-NEXT: addi a1, a1, 1639
|
|
; RV64IMZB-NEXT: mul a0, a0, a1
|
|
; RV64IMZB-NEXT: srli a1, a0, 63
|
|
; RV64IMZB-NEXT: srai a0, a0, 17
|
|
; RV64IMZB-NEXT: add a0, a0, a1
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i16 %a, 5
|
|
ret i16 %1
|
|
}
|
|
|
|
define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv16_constant_add_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a1, a0, 16
|
|
; RV32IM-NEXT: lui a2, 1048569
|
|
; RV32IM-NEXT: srai a1, a1, 16
|
|
; RV32IM-NEXT: addi a2, a2, -1911
|
|
; RV32IM-NEXT: mul a1, a1, a2
|
|
; RV32IM-NEXT: srli a1, a1, 16
|
|
; RV32IM-NEXT: add a0, a1, a0
|
|
; RV32IM-NEXT: slli a0, a0, 16
|
|
; RV32IM-NEXT: srli a1, a0, 31
|
|
; RV32IM-NEXT: srai a0, a0, 19
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv16_constant_add_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.h a1, a0
|
|
; RV32IMZB-NEXT: lui a2, 1048569
|
|
; RV32IMZB-NEXT: addi a2, a2, -1911
|
|
; RV32IMZB-NEXT: mul a1, a1, a2
|
|
; RV32IMZB-NEXT: srli a1, a1, 16
|
|
; RV32IMZB-NEXT: add a0, a1, a0
|
|
; RV32IMZB-NEXT: slli a0, a0, 16
|
|
; RV32IMZB-NEXT: srli a1, a0, 31
|
|
; RV32IMZB-NEXT: srai a0, a0, 19
|
|
; RV32IMZB-NEXT: add a0, a0, a1
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv16_constant_add_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a1, a0, 48
|
|
; RV64IM-NEXT: lui a2, 1048569
|
|
; RV64IM-NEXT: srai a1, a1, 48
|
|
; RV64IM-NEXT: addi a2, a2, -1911
|
|
; RV64IM-NEXT: mul a1, a1, a2
|
|
; RV64IM-NEXT: srli a1, a1, 16
|
|
; RV64IM-NEXT: add a0, a1, a0
|
|
; RV64IM-NEXT: slli a0, a0, 48
|
|
; RV64IM-NEXT: srli a1, a0, 63
|
|
; RV64IM-NEXT: srai a0, a0, 51
|
|
; RV64IM-NEXT: add a0, a0, a1
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv16_constant_add_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.h a1, a0
|
|
; RV64IMZB-NEXT: lui a2, 1048569
|
|
; RV64IMZB-NEXT: addi a2, a2, -1911
|
|
; RV64IMZB-NEXT: mul a1, a1, a2
|
|
; RV64IMZB-NEXT: srli a1, a1, 16
|
|
; RV64IMZB-NEXT: add a0, a1, a0
|
|
; RV64IMZB-NEXT: slli a0, a0, 48
|
|
; RV64IMZB-NEXT: srli a1, a0, 63
|
|
; RV64IMZB-NEXT: srai a0, a0, 51
|
|
; RV64IMZB-NEXT: add a0, a0, a1
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i16 %a, 15
|
|
ret i16 %1
|
|
}
|
|
|
|
define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
|
|
; RV32IM-LABEL: sdiv16_constant_sub_srai:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a1, a0, 16
|
|
; RV32IM-NEXT: lui a2, 7
|
|
; RV32IM-NEXT: srai a1, a1, 16
|
|
; RV32IM-NEXT: addi a2, a2, 1911
|
|
; RV32IM-NEXT: mul a1, a1, a2
|
|
; RV32IM-NEXT: srli a1, a1, 16
|
|
; RV32IM-NEXT: sub a1, a1, a0
|
|
; RV32IM-NEXT: slli a1, a1, 16
|
|
; RV32IM-NEXT: srli a0, a1, 31
|
|
; RV32IM-NEXT: srai a1, a1, 19
|
|
; RV32IM-NEXT: add a0, a1, a0
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMZB-LABEL: sdiv16_constant_sub_srai:
|
|
; RV32IMZB: # %bb.0:
|
|
; RV32IMZB-NEXT: sext.h a1, a0
|
|
; RV32IMZB-NEXT: lui a2, 7
|
|
; RV32IMZB-NEXT: addi a2, a2, 1911
|
|
; RV32IMZB-NEXT: mul a1, a1, a2
|
|
; RV32IMZB-NEXT: srli a1, a1, 16
|
|
; RV32IMZB-NEXT: sub a1, a1, a0
|
|
; RV32IMZB-NEXT: slli a1, a1, 16
|
|
; RV32IMZB-NEXT: srli a0, a1, 31
|
|
; RV32IMZB-NEXT: srai a1, a1, 19
|
|
; RV32IMZB-NEXT: add a0, a1, a0
|
|
; RV32IMZB-NEXT: ret
|
|
;
|
|
; RV64IM-LABEL: sdiv16_constant_sub_srai:
|
|
; RV64IM: # %bb.0:
|
|
; RV64IM-NEXT: slli a1, a0, 48
|
|
; RV64IM-NEXT: lui a2, 7
|
|
; RV64IM-NEXT: srai a1, a1, 48
|
|
; RV64IM-NEXT: addi a2, a2, 1911
|
|
; RV64IM-NEXT: mul a1, a1, a2
|
|
; RV64IM-NEXT: srli a1, a1, 16
|
|
; RV64IM-NEXT: sub a1, a1, a0
|
|
; RV64IM-NEXT: slli a1, a1, 48
|
|
; RV64IM-NEXT: srli a0, a1, 63
|
|
; RV64IM-NEXT: srai a1, a1, 51
|
|
; RV64IM-NEXT: add a0, a1, a0
|
|
; RV64IM-NEXT: ret
|
|
;
|
|
; RV64IMZB-LABEL: sdiv16_constant_sub_srai:
|
|
; RV64IMZB: # %bb.0:
|
|
; RV64IMZB-NEXT: sext.h a1, a0
|
|
; RV64IMZB-NEXT: lui a2, 7
|
|
; RV64IMZB-NEXT: addi a2, a2, 1911
|
|
; RV64IMZB-NEXT: mul a1, a1, a2
|
|
; RV64IMZB-NEXT: srli a1, a1, 16
|
|
; RV64IMZB-NEXT: sub a1, a1, a0
|
|
; RV64IMZB-NEXT: slli a1, a1, 48
|
|
; RV64IMZB-NEXT: srli a0, a1, 63
|
|
; RV64IMZB-NEXT: srai a1, a1, 51
|
|
; RV64IMZB-NEXT: add a0, a1, a0
|
|
; RV64IMZB-NEXT: ret
|
|
%1 = sdiv i16 %a, -15
|
|
ret i16 %1
|
|
}
|