derek.holloway
7502bf64a4
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97 lines
3.5 KiB
LLVM
97 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV64F %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV64F %s
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;; `.insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is
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;; the raw encoding for `fadd.s`
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@gf = external global float
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define float @constraint_f_modifier_N_float(float %a) nounwind {
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; RV32F-LABEL: constraint_f_modifier_N_float:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, %hi(gf)
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; RV32F-NEXT: flw fa5, %lo(gf)(a1)
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; RV32F-NEXT: fmv.w.x fa4, a0
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; RV32F-NEXT: #APP
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; RV32F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fmv.x.w a0, fa5
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_modifier_N_float:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gf)
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; RV64F-NEXT: flw fa5, %lo(gf)(a1)
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; RV64F-NEXT: fmv.w.x fa4, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.w a0, fa5
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; RV64F-NEXT: ret
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%1 = load float, ptr @gf
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%2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(float %a, float %1)
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ret float %2
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}
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define float @constraint_cf_modifier_N_float(float %a) nounwind {
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; RV32F-LABEL: constraint_cf_modifier_N_float:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, %hi(gf)
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; RV32F-NEXT: flw fa5, %lo(gf)(a1)
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; RV32F-NEXT: fmv.w.x fa4, a0
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; RV32F-NEXT: #APP
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; RV32F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fmv.x.w a0, fa5
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_cf_modifier_N_float:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gf)
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; RV64F-NEXT: flw fa5, %lo(gf)(a1)
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; RV64F-NEXT: fmv.w.x fa4, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.w a0, fa5
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; RV64F-NEXT: ret
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%1 = load float, ptr @gf
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%2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(float %a, float %1)
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ret float %2
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}
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define float @modifier_N_float_abi_name(float %a) nounwind {
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; RV32F-LABEL: modifier_N_float_abi_name:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, %hi(gf)
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; RV32F-NEXT: flw fs0, %lo(gf)(a1)
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; RV32F-NEXT: fmv.w.x fa0, a0
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; RV32F-NEXT: #APP
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; RV32F-NEXT: .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fmv.x.w a0, ft0
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: modifier_N_float_abi_name:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gf)
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; RV64F-NEXT: flw fs0, %lo(gf)(a1)
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; RV64F-NEXT: fmv.w.x fa0, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.w a0, ft0
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; RV64F-NEXT: ret
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%1 = load float, ptr @gf
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%2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa0},{fs0}"(float %a, float %1)
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ret float %2
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}
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