derek.holloway
7502bf64a4
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69 lines
2.2 KiB
LLVM
69 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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define <vscale x 1 x i8> @constraint_vr(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind {
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; RV32I-LABEL: constraint_vr:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: vadd.vv v8, v8, v9
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_vr:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: vadd.vv v8, v8, v9
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(
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<vscale x 1 x i8> %0, <vscale x 1 x i8> %1)
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind {
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; RV32I-LABEL: constraint_vd:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: vadd.vv v8, v8, v9
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_vd:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: vadd.vv v8, v8, v9
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(
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<vscale x 1 x i8> %0, <vscale x 1 x i8> %1)
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
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; RV32I-LABEL: constraint_vm:
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; RV32I: # %bb.0:
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; RV32I-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32I-NEXT: vmv1r.v v9, v0
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; RV32I-NEXT: vmv1r.v v0, v8
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; RV32I-NEXT: #APP
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; RV32I-NEXT: vadd.vv v0, v9, v0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_vm:
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; RV64I: # %bb.0:
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; RV64I-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64I-NEXT: vmv1r.v v9, v0
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; RV64I-NEXT: vmv1r.v v0, v8
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; RV64I-NEXT: #APP
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; RV64I-NEXT: vadd.vv v0, v9, v0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%a = tail call <vscale x 1 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"(
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<vscale x 1 x i1> %0, <vscale x 1 x i1> %1)
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ret <vscale x 1 x i1> %a
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}
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