derek.holloway
7502bf64a4
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267 lines
10 KiB
LLVM
267 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d < %s | FileCheck %s
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define <vscale x 4 x i1> @test_full_pinf_vs_pinf(<vscale x 4 x float> nofpclass(pinf) %a) {
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; CHECK-LABEL: test_full_pinf_vs_pinf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 512)
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @test_full_fabs_nan_vs_nan(<vscale x 4 x float> nofpclass(nan) %a) {
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; CHECK-LABEL: test_full_fabs_nan_vs_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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%abs = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %a)
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %abs, i32 3)
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @test_partial_nan_from_nan_pinf(<vscale x 4 x float> nofpclass(nan) %a) {
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; CHECK-LABEL: test_partial_nan_from_nan_pinf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 128
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 515)
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @test_partial_pinf_from_inf(<vscale x 4 x float> nofpclass(pinf) %a) {
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; CHECK-LABEL: test_partial_pinf_from_inf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 64
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 768)
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @test_no_overlap_pinf_vs_nan(<vscale x 4 x float> nofpclass(pinf) %a) {
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; CHECK-LABEL: test_no_overlap_pinf_vs_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 3)
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @test_no_overlap_nan_vs_pinf(<vscale x 4 x float> nofpclass(nan) %a) {
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; CHECK-LABEL: test_no_overlap_nan_vs_pinf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 128
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %a, i32 512)
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ret <vscale x 4 x i1> %class
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}
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; Fixed vector vselect tests
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define <4 x i1> @vselect_both_nevernan(<4 x i1> %cond, <4 x float> nofpclass(nan) %a, <4 x float> nofpclass(nan) %b) {
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; CHECK-LABEL: vselect_both_nevernan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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%sel = select <4 x i1> %cond, <4 x float> %a, <4 x float> %b
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%class = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %sel, i32 3) ; 0x3 = "nan"
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ret <4 x i1> %class
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}
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define <4 x i1> @vselect_both_neverzero(<4 x i1> %cond, <4 x float> nofpclass(zero) %a, <4 x float> nofpclass(zero) %b) {
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; CHECK-LABEL: vselect_both_neverzero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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%sel = select <4 x i1> %cond, <4 x float> %a, <4 x float> %b
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%class = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %sel, i32 96) ; 0x60 = "zero"
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ret <4 x i1> %class
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}
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; Scalable vector vselect tests
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define <vscale x 4 x i1> @vselect_both_neverinf(<vscale x 4 x i1> %cond, <vscale x 4 x float> nofpclass(inf) %a, <vscale x 4 x float> nofpclass(inf) %b) {
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; CHECK-LABEL: vselect_both_neverinf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sel, i32 516) ; 0x204 = "inf"
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @vselect_both_nevernan_query_naninf(<vscale x 4 x i1> %cond, <vscale x 4 x float> nofpclass(nan) %a, <vscale x 4 x float> nofpclass(nan) %b) {
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; CHECK-LABEL: vselect_both_nevernan_query_naninf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 129
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sel, i32 519) ; 0x207 = "nan|inf"
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @vselect_rhs_unknown(<vscale x 4 x i1> %cond, <vscale x 4 x float> nofpclass(nan) %a, <vscale x 4 x float> %b) {
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; CHECK-LABEL: vselect_rhs_unknown:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sel, i32 3) ; 0x3 = "nan"
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ret <vscale x 4 x i1> %class
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}
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define <vscale x 4 x i1> @vselect_lhs_unknown(<vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> nofpclass(nan) %b) {
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; CHECK-LABEL: vselect_lhs_unknown:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sel, i32 3) ; 0x3 = "nan"
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ret <vscale x 4 x i1> %class
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}
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define i1 @select_rhs_unknown(i1 %cond, float nofpclass(nan) %a, float %b) {
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; CHECK-LABEL: select_rhs_unknown:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: bnez a0, .LBB12_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.s fa0, fa1
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; CHECK-NEXT: .LBB12_2:
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; CHECK-NEXT: fclass.s a0, fa0
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; CHECK-NEXT: andi a0, a0, 768
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 3) ; 0x3 = "nan"
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ret i1 %class
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}
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define i1 @select_lhs_unknown(i1 %cond, float %a, float nofpclass(nan) %b) {
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; CHECK-LABEL: select_lhs_unknown:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: bnez a0, .LBB13_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.s fa0, fa1
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; CHECK-NEXT: .LBB13_2:
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; CHECK-NEXT: fclass.s a0, fa0
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; CHECK-NEXT: andi a0, a0, 768
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 3) ; 0x3 = "nan"
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ret i1 %class
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}
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define <vscale x 4 x i1> @vselect_asymmetric_nevernan_neverinf_query_nan(<vscale x 4 x i1> %cond, <vscale x 4 x float> nofpclass(nan) %a, <vscale x 4 x float> nofpclass(inf) %b) {
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; CHECK-LABEL: vselect_asymmetric_nevernan_neverinf_query_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%sel = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
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%class = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sel, i32 3) ; 0x3 = "nan"
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ret <vscale x 4 x i1> %class
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}
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; Scalar select tests
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define i1 @select_both_nevernan(i1 %cond, float nofpclass(nan) %a, float nofpclass(nan) %b) {
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; CHECK-LABEL: select_both_nevernan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 3) ; 0x3 = "nan"
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ret i1 %class
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}
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define i1 @select_both_neverinf(i1 %cond, float nofpclass(inf) %a, float nofpclass(inf) %b) {
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; CHECK-LABEL: select_both_neverinf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 516) ; 0x204 = "inf"
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ret i1 %class
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}
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define i1 @select_both_neverzero(i1 %cond, float nofpclass(zero) %a, float nofpclass(zero) %b) {
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; CHECK-LABEL: select_both_neverzero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 96) ; 0x60 = "zero"
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ret i1 %class
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}
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define i1 @select_asymmetric_nevernan_neverinf_query_nan(i1 %cond, float nofpclass(nan) %a, float nofpclass(inf) %b) {
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; CHECK-LABEL: select_asymmetric_nevernan_neverinf_query_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: bnez a0, .LBB18_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.s fa0, fa1
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; CHECK-NEXT: .LBB18_2:
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; CHECK-NEXT: fclass.s a0, fa0
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; CHECK-NEXT: andi a0, a0, 768
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 3) ; 0x3 = "nan"
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ret i1 %class
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}
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define i1 @select_asymmetric_nevernan_neverinf_query_inf(i1 %cond, float nofpclass(nan) %a, float nofpclass(inf) %b) {
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; CHECK-LABEL: select_asymmetric_nevernan_neverinf_query_inf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: bnez a0, .LBB19_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.s fa0, fa1
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; CHECK-NEXT: .LBB19_2:
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; CHECK-NEXT: fclass.s a0, fa0
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; CHECK-NEXT: andi a0, a0, 129
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%sel = select i1 %cond, float %a, float %b
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%class = call i1 @llvm.is.fpclass.f32(float %sel, i32 516) ; 0x204 = "inf"
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ret i1 %class
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}
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