derek.holloway
7502bf64a4
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175 lines
5.9 KiB
LLVM
175 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64I
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; This test case test the LocalStackSlotAllocation pass that use a base register
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; for the frame index that its offset is out-of-range (for RISC-V. the immediate
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; is 12 bits for the load store instruction (excludes vector load / store))
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define void @use_frame_base_reg() {
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; RV32I-LABEL: use_frame_base_reg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: addi a0, a0, 1712
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: .cfi_def_cfa_offset 100016
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: addi a0, a0, 1704
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lbu zero, 4(a0)
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; RV32I-NEXT: lbu zero, 0(a0)
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: addi a0, a0, 1712
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: use_frame_base_reg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: addi a0, a0, 1712
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; RV64I-NEXT: sub sp, sp, a0
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; RV64I-NEXT: .cfi_def_cfa_offset 100016
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: addi a0, a0, 1704
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; RV64I-NEXT: add a0, sp, a0
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; RV64I-NEXT: lbu zero, 4(a0)
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; RV64I-NEXT: lbu zero, 0(a0)
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: addi a0, a0, 1712
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; RV64I-NEXT: add sp, sp, a0
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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%va = alloca i8, align 4
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%va1 = alloca i8, align 4
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%large = alloca [ 100000 x i8 ]
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%argp.cur = load volatile i8, ptr %va, align 4
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%argp.next = load volatile i8, ptr %va1, align 4
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ret void
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}
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; Test containing a load with its own local offset. Make sure isFrameOffsetLegal
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; considers it and creates a virtual base register.
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define void @load_with_offset() {
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; RV32I-LABEL: load_with_offset:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -2048
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; RV32I-NEXT: addi sp, sp, -464
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; RV32I-NEXT: .cfi_def_cfa_offset 2512
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; RV32I-NEXT: addi a0, sp, 2012
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; RV32I-NEXT: lbu a1, 0(a0)
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: addi sp, sp, 2032
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; RV32I-NEXT: addi sp, sp, 480
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_with_offset:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -2048
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; RV64I-NEXT: addi sp, sp, -464
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; RV64I-NEXT: .cfi_def_cfa_offset 2512
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; RV64I-NEXT: addi a0, sp, 2012
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; RV64I-NEXT: lbu a1, 0(a0)
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; RV64I-NEXT: sb a1, 0(a0)
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; RV64I-NEXT: addi sp, sp, 2032
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; RV64I-NEXT: addi sp, sp, 480
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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%va = alloca [2500 x i8], align 4
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%va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 2000
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%load = load volatile i8, ptr %va_gep, align 4
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store volatile i8 %load, ptr %va_gep, align 4
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ret void
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}
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; Test containing a load with its own local offset that is smaller than the
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; previous test case. Make sure we don't create a virtual base register.
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define void @load_with_offset2() {
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; RV32I-LABEL: load_with_offset2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -2048
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; RV32I-NEXT: addi sp, sp, -464
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; RV32I-NEXT: .cfi_def_cfa_offset 2512
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; RV32I-NEXT: lbu a0, 1412(sp)
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; RV32I-NEXT: sb a0, 1412(sp)
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; RV32I-NEXT: addi sp, sp, 2032
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; RV32I-NEXT: addi sp, sp, 480
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_with_offset2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -2048
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; RV64I-NEXT: addi sp, sp, -464
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; RV64I-NEXT: .cfi_def_cfa_offset 2512
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; RV64I-NEXT: lbu a0, 1412(sp)
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; RV64I-NEXT: sb a0, 1412(sp)
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; RV64I-NEXT: addi sp, sp, 2032
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; RV64I-NEXT: addi sp, sp, 480
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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%va = alloca [2500 x i8], align 4
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%va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 1400
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%load = load volatile i8, ptr %va_gep, align 4
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store volatile i8 %load, ptr %va_gep, align 4
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ret void
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}
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define void @frame_pointer() "frame-pointer"="all" {
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; RV32I-LABEL: frame_pointer:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -2032
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; RV32I-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
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; RV32I-NEXT: .cfi_offset ra, -4
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; RV32I-NEXT: .cfi_offset s0, -8
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; RV32I-NEXT: addi s0, sp, 2032
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; RV32I-NEXT: .cfi_def_cfa s0, 0
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; RV32I-NEXT: addi sp, sp, -480
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; RV32I-NEXT: lbu a0, -1960(s0)
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; RV32I-NEXT: sb a0, -1960(s0)
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; RV32I-NEXT: addi sp, sp, 480
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; RV32I-NEXT: .cfi_def_cfa sp, 2032
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; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
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; RV32I-NEXT: .cfi_restore ra
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; RV32I-NEXT: .cfi_restore s0
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; RV32I-NEXT: addi sp, sp, 2032
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: frame_pointer:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -2032
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; RV64I-NEXT: .cfi_def_cfa_offset 2032
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; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
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; RV64I-NEXT: .cfi_offset ra, -8
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; RV64I-NEXT: .cfi_offset s0, -16
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; RV64I-NEXT: addi s0, sp, 2032
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; RV64I-NEXT: .cfi_def_cfa s0, 0
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; RV64I-NEXT: addi sp, sp, -496
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; RV64I-NEXT: addi a0, s0, -1972
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; RV64I-NEXT: lbu a1, 0(a0)
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; RV64I-NEXT: sb a1, 0(a0)
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; RV64I-NEXT: addi sp, sp, 496
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; RV64I-NEXT: .cfi_def_cfa sp, 2032
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; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
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; RV64I-NEXT: .cfi_restore ra
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; RV64I-NEXT: .cfi_restore s0
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; RV64I-NEXT: addi sp, sp, 2032
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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%va = alloca [2500 x i8], align 4
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%va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 552
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%load = load volatile i8, ptr %va_gep, align 4
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store volatile i8 %load, ptr %va_gep, align 4
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ret void
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}
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