TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/machine-combiner.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \
# RUN:   -verify-machineinstrs | FileCheck %s

--- |
  source_filename = "test.ll"
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
  target triple = "riscv64"

  define void @foo(ptr %0, ptr %1, float %2, float %3, ptr %4, ptr %5) #0 {
    %7 = load float, ptr %0, align 4
    %8 = load float, ptr %1, align 4
    %9 = fmul fast float %8, %7
    %10 = fadd fast float %9, %2
    store float %10, ptr %4, align 4
    %11 = fsub fast float %3, %9
    store float %11, ptr %5, align 4
    ret void
  }

  attributes #0 = { "target-features"="+f" }

...
---
name:            foo
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: fpr32 }
  - { id: 3, class: fpr32 }
  - { id: 4, class: gpr }
  - { id: 5, class: gpr }
  - { id: 6, class: fpr32 }
  - { id: 7, class: fpr32 }
  - { id: 8, class: fpr32 }
  - { id: 9, class: fpr32 }
  - { id: 10, class: fpr32 }
liveins:
  - { reg: '$x10', virtual-reg: '%0' }
  - { reg: '$x11', virtual-reg: '%1' }
  - { reg: '$f10_f', virtual-reg: '%2' }
  - { reg: '$f11_f', virtual-reg: '%3' }
  - { reg: '$x12', virtual-reg: '%4' }
  - { reg: '$x13', virtual-reg: '%5' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo:
  varArgsFrameIndex: 0
  varArgsSaveSize: 0
body:             |
  bb.0 (%ir-block.6):
    liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13

    ; CHECK-LABEL: name: foo
    ; CHECK: liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY5]], 0 :: (load (s32) from %ir.0)
    ; CHECK-NEXT: [[FLW1:%[0-9]+]]:fpr32 = FLW [[COPY4]], 0 :: (load (s32) from %ir.1)
    ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMADD_S [[FLW1]], [[FLW]], [[COPY3]], 7, implicit $frm
    ; CHECK-NEXT: FSW killed [[FMADD_S]], [[COPY1]], 0 :: (store (s32) into %ir.4)
    ; CHECK-NEXT: [[FNMSUB_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FNMSUB_S [[FLW1]], [[FLW]], [[COPY2]], 7, implicit $frm
    ; CHECK-NEXT: FSW killed [[FNMSUB_S]], [[COPY]], 0 :: (store (s32) into %ir.5)
    ; CHECK-NEXT: PseudoRET
    %5:gpr = COPY $x13
    %4:gpr = COPY $x12
    %3:fpr32 = COPY $f11_f
    %2:fpr32 = COPY $f10_f
    %1:gpr = COPY $x11
    %0:gpr = COPY $x10
    %6:fpr32 = FLW %0, 0 :: (load (s32) from %ir.0)
    %7:fpr32 = FLW %1, 0 :: (load (s32) from %ir.1)
    %8:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMUL_S killed %7, killed %6, 7, implicit $frm
    %9:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADD_S %8, %2, 7, implicit $frm
    FSW killed %9, %4, 0 :: (store (s32) into %ir.4)
    %10:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FSUB_S %3, %8, 7, implicit $frm
    FSW killed %10, %5, 0 :: (store (s32) into %ir.5)
    PseudoRET

...