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97 lines
3.8 KiB
YAML
97 lines
3.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV32I-MO %s
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV64I-MO %s
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# Position instructions are illegal to outline. The first instruction won't be outlined
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# because position instructions break the sequence.
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--- |
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define void @func1(i32 %a, i32 %b) { ret void }
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define void @func2(i32 %a, i32 %b) { ret void }
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define void @func3(i32 %a, i32 %b) { ret void }
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...
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---
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name: func1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func1
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
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; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: func1
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
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; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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EH_LABEL <mcsymbol .Ltmp0>
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func2
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
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; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: func2
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
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; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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GC_LABEL <mcsymbol .Ltmp1>
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func3
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
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; RV32I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: func3
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
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; RV64I-MO-NEXT: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x10, implicit $x11
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$x10 = ORI $x10, 1023
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ANNOTATION_LABEL <mcsymbol .Ltmp2>
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET
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