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55 lines
2.2 KiB
YAML
55 lines
2.2 KiB
YAML
# Check that modifying X5 register is not a problem for machine outliner
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s
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--- |
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define i32 @outline_tail_1(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_tail_2(i32 %a, i32 %b) { ret i32 0 }
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...
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---
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name: outline_tail_1
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tracksRegLiveness: true
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isOutlined: false
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body: |
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bb.0:
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liveins: $x10, $x11, $x5
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; RV32I-MO-LABEL: name: outline_tail_1
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; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: outline_tail_1
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; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x10 = ADD $x10, $x5
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: outline_tail_2
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tracksRegLiveness: true
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isOutlined: false
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body: |
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bb.0:
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liveins: $x10, $x11, $x5
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; RV32I-MO-LABEL: name: outline_tail_2
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; RV32I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11
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;
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; RV64I-MO-LABEL: name: outline_tail_2
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; RV64I-MO: PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x10 = ADD $x10, $x5
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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# CHECK-LABEL: name: OUTLINED_FUNCTION_0
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# CHECK: isOutlined: true
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