derek.holloway
7502bf64a4
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83 lines
2.3 KiB
LLVM
83 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s
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define i32 @signed(i32 %0, ptr %1) {
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; CHECK-LABEL: signed:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sraiw a2, a0, 31
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; CHECK-NEXT: srliw a2, a2, 24
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; CHECK-NEXT: add a2, a0, a2
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; CHECK-NEXT: andi a2, a2, -256
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; CHECK-NEXT: sub a2, a0, a2
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; CHECK-NEXT: sraiw a0, a0, 8
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; CHECK-NEXT: sw a2, 0(a1)
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; CHECK-NEXT: ret
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%rem = srem i32 %0, 256
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store i32 %rem, ptr %1, align 4
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%div = sdiv exact i32 %0, 256
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ret i32 %div
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}
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define i32 @unsigned(i32 %0, ptr %1) {
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; CHECK-LABEL: unsigned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a2, a0, 32
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; CHECK-NEXT: lui a3, 699051
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; CHECK-NEXT: addi a3, a3, -1365
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; CHECK-NEXT: slli a4, a3, 32
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; CHECK-NEXT: mulhu a2, a2, a4
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; CHECK-NEXT: srli a2, a2, 36
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; CHECK-NEXT: slli a4, a2, 3
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; CHECK-NEXT: slli a2, a2, 4
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; CHECK-NEXT: add a2, a2, a4
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; CHECK-NEXT: srliw a4, a0, 3
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; CHECK-NEXT: sub a2, a0, a2
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; CHECK-NEXT: mulw a0, a4, a3
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; CHECK-NEXT: sw a2, 0(a1)
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; CHECK-NEXT: ret
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%rem = urem i32 %0, 24
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store i32 %rem, ptr %1, align 4
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%div = udiv exact i32 %0, 24
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ret i32 %div
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}
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define i32 @signed_div_first(i32 %0, ptr %1) {
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; CHECK-LABEL: signed_div_first:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sraiw a2, a0, 31
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; CHECK-NEXT: srliw a2, a2, 24
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; CHECK-NEXT: add a3, a0, a2
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; CHECK-NEXT: sraiw a2, a3, 8
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; CHECK-NEXT: andi a3, a3, -256
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; CHECK-NEXT: sub a0, a0, a3
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; CHECK-NEXT: sw a0, 0(a1)
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%div = sdiv exact i32 %0, 256
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%rem = srem i32 %0, 256
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store i32 %rem, ptr %1, align 4
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ret i32 %div
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}
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define i32 @unsigned_div_first(i32 %0, ptr %1) {
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; CHECK-LABEL: unsigned_div_first:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a2, a0, 32
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; CHECK-NEXT: lui a3, 699051
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; CHECK-NEXT: addi a3, a3, -1365
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; CHECK-NEXT: slli a3, a3, 32
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; CHECK-NEXT: mulhu a2, a2, a3
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; CHECK-NEXT: srli a2, a2, 36
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; CHECK-NEXT: slli a3, a2, 3
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; CHECK-NEXT: slli a4, a2, 4
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; CHECK-NEXT: add a3, a4, a3
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; CHECK-NEXT: sub a0, a0, a3
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; CHECK-NEXT: sw a0, 0(a1)
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%div = udiv exact i32 %0, 24
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%rem = urem i32 %0, 24
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store i32 %rem, ptr %1, align 4
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ret i32 %div
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}
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