derek.holloway
7502bf64a4
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41 lines
1.2 KiB
LLVM
41 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
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; These two loads will CSE, we need to conservatively combine the range
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; metadata. The final assembly should not contain an OR.
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define i32 @f(ptr %p) {
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; CHECK-LABEL: f:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a0, 0(a0)
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; CHECK-NEXT: lui a1, 294471
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; CHECK-NEXT: addi a1, a1, 1064
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; CHECK-NEXT: addw a0, a0, a1
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; CHECK-NEXT: ret
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%load = load i32, ptr %p, align 4, !range !0
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%load2 = load i32, ptr %p, align 4
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%add = add i32 1206154280, %load2
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ret i32 %add
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}
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; The mul and getelementptr will get removed in DAGCombine causing the loads
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; to CSE after they are created.
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define i32 @test(ptr %p, i32 %x, ptr %q) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: lui a0, 294471
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; CHECK-NEXT: addi a0, a0, 1064
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; CHECK-NEXT: addw a0, a1, a0
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; CHECK-NEXT: sw a1, 0(a2)
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; CHECK-NEXT: ret
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%load = load i32, ptr %p, align 4, !range !0
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%mul = mul i32 0, %x
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%a = getelementptr i32, ptr %p, i32 %mul
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%load2 = load i32, ptr %a, align 4
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%add = add i32 1206154280, %load2
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store i32 %load, ptr %q
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ret i32 %add
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}
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!0 = !{i32 1, i32 2, i32 3, i32 4}
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