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117 lines
5.4 KiB
YAML
117 lines
5.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc %s -mtriple=riscv64 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - | FileCheck %s
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---
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name: foo
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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localFrameSize: 4
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stack:
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- { id: 0, size: 1, alignment: 4, local-offset: -4 }
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machineFunctionInfo:
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varArgsFrameIndex: 0
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varArgsSaveSize: 0
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body: |
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bb.0.entry:
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; To trick stack-slot-colouring to run its dead-store-elimination phase,
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; which is at fault, we need the register allocator to run, and spill in two
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; places that can have their slots merged. Achieve this by volatile-loading
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; data into all allocatable GPRs except $x31. Then, volatile storing them
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; later, leaving regalloc only $x31 to play with in the middle.
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$x1 = LW %stack.0, 0 :: (volatile load (s32))
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$x5 = LW %stack.0, 0 :: (volatile load (s32))
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$x6 = LW %stack.0, 0 :: (volatile load (s32))
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$x7 = LW %stack.0, 0 :: (volatile load (s32))
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$x8 = LW %stack.0, 0 :: (volatile load (s32))
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$x9 = LW %stack.0, 0 :: (volatile load (s32))
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$x10 = LW %stack.0, 0 :: (volatile load (s32))
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$x11 = LW %stack.0, 0 :: (volatile load (s32))
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$x12 = LW %stack.0, 0 :: (volatile load (s32))
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$x13 = LW %stack.0, 0 :: (volatile load (s32))
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$x14 = LW %stack.0, 0 :: (volatile load (s32))
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$x15 = LW %stack.0, 0 :: (volatile load (s32))
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$x16 = LW %stack.0, 0 :: (volatile load (s32))
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$x17 = LW %stack.0, 0 :: (volatile load (s32))
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$x18 = LW %stack.0, 0 :: (volatile load (s32))
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$x19 = LW %stack.0, 0 :: (volatile load (s32))
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$x20 = LW %stack.0, 0 :: (volatile load (s32))
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$x21 = LW %stack.0, 0 :: (volatile load (s32))
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$x22 = LW %stack.0, 0 :: (volatile load (s32))
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$x23 = LW %stack.0, 0 :: (volatile load (s32))
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$x24 = LW %stack.0, 0 :: (volatile load (s32))
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$x25 = LW %stack.0, 0 :: (volatile load (s32))
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$x26 = LW %stack.0, 0 :: (volatile load (s32))
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$x27 = LW %stack.0, 0 :: (volatile load (s32))
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$x28 = LW %stack.0, 0 :: (volatile load (s32))
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$x29 = LW %stack.0, 0 :: (volatile load (s32))
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$x30 = LW %stack.0, 0 :: (volatile load (s32))
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; Force the first spill.
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%0:gpr = LW %stack.0, 0 :: (volatile load (s32))
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%1:gpr = LW %stack.0, 0 :: (volatile load (s32))
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SW %1, %stack.0, 0 :: (volatile store (s32))
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SW %0, %stack.0, 0 :: (volatile store (s32))
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; CHECK: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
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; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1)
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; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
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; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))
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; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1)
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; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))
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; stack-slot-coloring doesn't know that a write to $x0 is discarded.
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dead $x0 = LW %stack.0, 0 :: (volatile load (s32))
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; This stores 0 rather than the result of the preceding load since $x0
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; is special.
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; We don't want this store to be deleted.
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SW $x0, %stack.0, 0 :: (volatile store (s32))
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; CHECK-NEXT: dead $x0 = LW %stack.0, 0 :: (volatile load (s32))
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; CHECK-NEXT: SW $x0, %stack.0, 0 :: (volatile store (s32))
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; Force a second spill
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%2:gpr = LW %stack.0, 0 :: (volatile load (s32))
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%3:gpr = LW %stack.0, 0 :: (volatile load (s32))
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SW %3, %stack.0, 0 :: (volatile store (s32))
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SW %2, %stack.0, 0 :: (volatile store (s32))
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; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
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; CHECK-NEXT: SD killed renamable $x31, %stack.1, 0 :: (store (s64) into %stack.1)
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; CHECK-NEXT: renamable $x31 = LW %stack.0, 0 :: (volatile load (s32))
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; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))
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; CHECK-NEXT: renamable $x31 = LD %stack.1, 0 :: (load (s64) from %stack.1)
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; CHECK-NEXT: SW killed renamable $x31, %stack.0, 0 :: (volatile store (s32))
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SW $x1, %stack.0, 0 :: (volatile store (s32))
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SW $x5, %stack.0, 0 :: (volatile store (s32))
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SW $x6, %stack.0, 0 :: (volatile store (s32))
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SW $x7, %stack.0, 0 :: (volatile store (s32))
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SW $x8, %stack.0, 0 :: (volatile store (s32))
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SW $x9, %stack.0, 0 :: (volatile store (s32))
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SW $x10, %stack.0, 0 :: (volatile store (s32))
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SW $x11, %stack.0, 0 :: (volatile store (s32))
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SW $x12, %stack.0, 0 :: (volatile store (s32))
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SW $x13, %stack.0, 0 :: (volatile store (s32))
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SW $x14, %stack.0, 0 :: (volatile store (s32))
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SW $x15, %stack.0, 0 :: (volatile store (s32))
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SW $x16, %stack.0, 0 :: (volatile store (s32))
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SW $x17, %stack.0, 0 :: (volatile store (s32))
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SW $x18, %stack.0, 0 :: (volatile store (s32))
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SW $x19, %stack.0, 0 :: (volatile store (s32))
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SW $x20, %stack.0, 0 :: (volatile store (s32))
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SW $x21, %stack.0, 0 :: (volatile store (s32))
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SW $x22, %stack.0, 0 :: (volatile store (s32))
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SW $x23, %stack.0, 0 :: (volatile store (s32))
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SW $x24, %stack.0, 0 :: (volatile store (s32))
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SW $x25, %stack.0, 0 :: (volatile store (s32))
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SW $x26, %stack.0, 0 :: (volatile store (s32))
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SW $x27, %stack.0, 0 :: (volatile store (s32))
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SW $x28, %stack.0, 0 :: (volatile store (s32))
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SW $x29, %stack.0, 0 :: (volatile store (s32))
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SW $x30, %stack.0, 0 :: (volatile store (s32))
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PseudoRET
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...
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