derek.holloway
7502bf64a4
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21 lines
889 B
LLVM
21 lines
889 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32-unknown-linux-gnu < %s | FileCheck %s
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; Dag-combine used to improperly combine a vector vselect of 0 and 2 into
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; 2 + condition(0/1) because one of the two args was transformed from an i32->i64.
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define i16 @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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entry:
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%insert.0 = insertelement <4 x i16> zeroinitializer, i16 2, i64 0
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%all.two = shufflevector <4 x i16> %insert.0, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer
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%sel.0 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> zeroinitializer, <4 x i16> %all.two
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%mul.0 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %sel.0)
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ret i16 %mul.0
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}
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