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65 lines
2.0 KiB
LLVM
65 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s
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define i32 @PR95271(ptr %p) {
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; RV32I-LABEL: PR95271:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: lui a1, 349525
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; RV32I-NEXT: addi a1, a1, 1365
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: srli a2, a0, 1
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; RV32I-NEXT: and a1, a2, a1
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; RV32I-NEXT: lui a2, 209715
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; RV32I-NEXT: addi a2, a2, 819
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: and a1, a0, a2
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; RV32I-NEXT: srli a0, a0, 2
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: lui a2, 61681
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: srli a1, a0, 4
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: addi a1, a2, -241
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 16
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srli a0, a0, 24
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: PR95271:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: lui a1, 349525
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; RV64I-NEXT: addi a1, a1, 1365
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; RV64I-NEXT: addi a2, a0, 1
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; RV64I-NEXT: srli a2, a2, 1
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; RV64I-NEXT: and a1, a2, a1
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; RV64I-NEXT: lui a2, 209715
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; RV64I-NEXT: addi a2, a2, 819
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; RV64I-NEXT: addiw a0, a0, 1
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; RV64I-NEXT: sub a0, a0, a1
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; RV64I-NEXT: and a1, a0, a2
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; RV64I-NEXT: srli a0, a0, 2
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: lui a2, 61681
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: srli a1, a0, 4
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: addi a1, a2, -241
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: slli a1, a0, 8
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a1, a0, 16
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: srliw a0, a0, 24
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; RV64I-NEXT: ret
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%load = load i32, ptr %p, align 4
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%inc = add i32 %load, 1
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%pop = tail call i32 @llvm.ctpop.i32(i32 %inc)
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ret i32 %pop
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}
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