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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64XTHEADBB,RV64XTHEADBB-NOB
; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb,+b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64XTHEADBB,RV64XTHEADBB-B
define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-LABEL: ctlz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB0_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, a2, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: ctlz_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -32
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: ctlz_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: clzw a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %1
}
define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-LABEL: log2_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB1_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, a2, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: .LBB1_3: # %cond.end
; RV64I-NEXT: li a1, 31
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: log2_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 63
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: log2_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: clzw a0, a0
; RV64XTHEADBB-B-NEXT: li a1, 31
; RV64XTHEADBB-B-NEXT: sub a0, a1, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
%2 = sub i32 31, %1
ret i32 %2
}
define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-LABEL: log2_ceil_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a1, a0, -1
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: li a2, 32
; RV64I-NEXT: beqz a1, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a2, a1, 1
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: addi a2, a3, 1365
; RV64I-NEXT: srliw a3, a1, 2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 4
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 8
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 16
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: srli a3, a1, 1
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: sub a1, a1, a2
; RV64I-NEXT: and a2, a1, a3
; RV64I-NEXT: srli a1, a1, 2
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: srli a2, a1, 4
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: addi a2, a3, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a2, a1, 8
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: srliw a2, a1, 24
; RV64I-NEXT: .LBB2_2: # %cond.end
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: log2_ceil_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -1
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 64
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: log2_ceil_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: addi a0, a0, -1
; RV64XTHEADBB-B-NEXT: clzw a0, a0
; RV64XTHEADBB-B-NEXT: li a1, 32
; RV64XTHEADBB-B-NEXT: sub a0, a1, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = sub i32 %a, 1
%2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
%3 = sub i32 32, %2
ret i32 %3
}
define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-LABEL: findLastSet_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a1, a0, a1
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: srliw a3, a1, 2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 4
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 8
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 16
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: srli a3, a1, 1
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: sub a1, a1, a2
; RV64I-NEXT: and a2, a1, a3
; RV64I-NEXT: srli a1, a1, 2
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: srli a2, a1, 4
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a2, a1, 8
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a1, 16
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: srliw a1, a1, 24
; RV64I-NEXT: xori a1, a1, 31
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: findLastSet_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: slli a1, a0, 32
; RV64XTHEADBB-NOB-NEXT: snez a0, a0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a1, a1
; RV64XTHEADBB-NOB-NEXT: xori a1, a1, 31
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -1
; RV64XTHEADBB-NOB-NEXT: or a0, a0, a1
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: findLastSet_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: clzw a1, a0
; RV64XTHEADBB-B-NEXT: snez a0, a0
; RV64XTHEADBB-B-NEXT: xori a1, a1, 31
; RV64XTHEADBB-B-NEXT: addi a0, a0, -1
; RV64XTHEADBB-B-NEXT: or a0, a0, a1
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
%2 = xor i32 31, %1
%3 = icmp eq i32 %a, 0
%4 = select i1 %3, i32 -1, i32 %2
ret i32 %4
}
define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-LABEL: ctlz_lshr_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 16
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, a2, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: ctlz_lshr_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: srliw a0, a0, 1
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -32
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: ctlz_lshr_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: srliw a0, a0, 1
; RV64XTHEADBB-B-NEXT: clzw a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = lshr i32 %a, 1
%2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
ret i32 %2
}
define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-LABEL: ctlz_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: addi a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: slli a3, a2, 32
; RV64I-NEXT: add a2, a2, a3
; RV64I-NEXT: srli a3, a0, 4
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srli a3, a0, 16
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srli a3, a0, 32
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a2, a3, 32
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: add a2, a3, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: li a0, 64
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: ctlz_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: ctlz_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: clz a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
ret i64 %1
}
define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-LABEL: cttz_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB6_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 6
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a0, 16
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 18
; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a4, a0, 4
; RV64I-NEXT: sub a4, a0, a4
; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: slli a4, a0, 14
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a0, a0, 27
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: cttz_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: beqz a0, .LBB6_2
; RV64XTHEADBB-NOB-NEXT: # %bb.1: # %cond.false
; RV64XTHEADBB-NOB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: and a0, a0, a1
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 64
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
; RV64XTHEADBB-NOB-NEXT: .LBB6_2:
; RV64XTHEADBB-NOB-NEXT: li a0, 32
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: cttz_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: ctzw a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %1
}
define signext i32 @cttz_zero_poison_i32(i32 signext %a) nounwind {
; RV64I-LABEL: cttz_zero_poison_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, a0, 6
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: slli a2, a0, 16
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 18
; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a4, a0, 4
; RV64I-NEXT: sub a4, a0, a4
; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: slli a4, a0, 14
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
; RV64I-NEXT: sub a2, a2, a4
; RV64I-NEXT: slli a0, a0, 27
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: cttz_zero_poison_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: and a0, a0, a1
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 64
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: cttz_zero_poison_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: ctzw a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
ret i32 %1
}
define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-LABEL: findFirstSet_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a1, 6
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
; RV64I-NEXT: add a2, a2, a3
; RV64I-NEXT: slli a3, a1, 16
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 18
; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: slli a5, a1, 4
; RV64I-NEXT: sub a5, a1, a5
; RV64I-NEXT: add a2, a5, a2
; RV64I-NEXT: slli a5, a1, 14
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: add a1, a3, a1
; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: srliw a1, a1, 27
; RV64I-NEXT: lui a2, %hi(.LCPI8_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_0)
; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: lbu a1, 0(a1)
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: findFirstSet_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a2, a0
; RV64XTHEADBB-NOB-NEXT: and a1, a2, a1
; RV64XTHEADBB-NOB-NEXT: li a2, 64
; RV64XTHEADBB-NOB-NEXT: snez a0, a0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a1, a1
; RV64XTHEADBB-NOB-NEXT: sub a2, a2, a1
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -1
; RV64XTHEADBB-NOB-NEXT: or a0, a0, a2
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: findFirstSet_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: ctzw a1, a0
; RV64XTHEADBB-B-NEXT: snez a0, a0
; RV64XTHEADBB-B-NEXT: addi a0, a0, -1
; RV64XTHEADBB-B-NEXT: or a0, a0, a1
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
%2 = icmp eq i32 %a, 0
%3 = select i1 %2, i32 -1, i32 %1
ret i32 %3
}
define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-LABEL: ffs_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a1, 6
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
; RV64I-NEXT: add a2, a2, a3
; RV64I-NEXT: slli a3, a1, 16
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 18
; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: slli a5, a1, 4
; RV64I-NEXT: sub a5, a1, a5
; RV64I-NEXT: add a2, a5, a2
; RV64I-NEXT: slli a5, a1, 14
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
; RV64I-NEXT: sub a3, a3, a5
; RV64I-NEXT: add a2, a2, a4
; RV64I-NEXT: lui a4, %hi(.LCPI9_0)
; RV64I-NEXT: addi a4, a4, %lo(.LCPI9_0)
; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a1, a3, a1
; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: srliw a1, a1, 27
; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: lbu a1, 0(a1)
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: ffs_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a2, a0
; RV64XTHEADBB-NOB-NEXT: and a1, a2, a1
; RV64XTHEADBB-NOB-NEXT: li a2, 65
; RV64XTHEADBB-NOB-NEXT: seqz a0, a0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a1, a1
; RV64XTHEADBB-NOB-NEXT: sub a2, a2, a1
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -1
; RV64XTHEADBB-NOB-NEXT: and a0, a0, a2
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: ffs_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: ctzw a1, a0
; RV64XTHEADBB-B-NEXT: seqz a0, a0
; RV64XTHEADBB-B-NEXT: addi a1, a1, 1
; RV64XTHEADBB-B-NEXT: addi a0, a0, -1
; RV64XTHEADBB-B-NEXT: and a0, a0, a1
; RV64XTHEADBB-B-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
%2 = add i32 %1, 1
%3 = icmp eq i32 %a, 0
%4 = select i1 %3, i32 0, i32 %2
ret i32 %4
}
define i64 @cttz_i64(i64 %a) nounwind {
; RV64I-LABEL: cttz_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB10_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: neg a1, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI10_0)
; RV64I-NEXT: ld a1, %lo(.LCPI10_0)(a1)
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 58
; RV64I-NEXT: lui a1, %hi(.LCPI10_1)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_1)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: li a0, 64
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: cttz_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: beqz a0, .LBB10_2
; RV64XTHEADBB-NOB-NEXT: # %bb.1: # %cond.false
; RV64XTHEADBB-NOB-NEXT: addi a1, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: and a0, a0, a1
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 64
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
; RV64XTHEADBB-NOB-NEXT: .LBB10_2:
; RV64XTHEADBB-NOB-NEXT: li a0, 64
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: cttz_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: ctz a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %1
}
define signext i32 @sexti1_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sexti1_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%shl = shl i32 %a, 31
%shr = ashr exact i32 %shl, 31
ret i32 %shr
}
define signext i32 @sexti1_i32_2(i1 %a) nounwind {
; RV64I-LABEL: sexti1_i32_2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i32_2:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%sext = sext i1 %a to i32
ret i32 %sext
}
; Make sure we don't use not+th.ext
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
; CHECK-LABEL: sexti1_i32_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: srli a0, a0, 63
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: ret
%icmp = icmp sgt i32 %a, -1
%sext = sext i1 %icmp to i8
ret i8 %sext
}
; Make sure we don't use seqz+th.ext instead of snez+addi
define signext i32 @sexti1_i32_setcc_2(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: sexti1_i32_setcc_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%icmp = icmp eq i32 %a, %b
%sext = sext i1 %icmp to i32
ret i32 %sext
}
; Make sure we don't use th.ext instead of neg.
define signext i32 @sexti1_i32_setcc_3(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: sexti1_i32_setcc_3:
; CHECK: # %bb.0:
; CHECK-NEXT: slt a0, a0, a1
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%icmp = icmp slt i32 %a, %b
%sext = sext i1 %icmp to i32
ret i32 %sext
}
define i64 @sexti1_i64(i64 %a) nounwind {
; RV64I-LABEL: sexti1_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%shl = shl i64 %a, 63
%shr = ashr exact i64 %shl, 63
ret i64 %shr
}
define i64 @sexti1_i64_2(i1 %a) nounwind {
; RV64I-LABEL: sexti1_i64_2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sexti1_i64_2:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
; RV64XTHEADBB-NEXT: ret
%sext = sext i1 %a to i64
ret i64 %sext
}
; Make sure we don't use not+th.ext
define zeroext i8 @sexti1_i64_setcc(i64 %a) {
; CHECK-LABEL: sexti1_i64_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: srli a0, a0, 63
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: ret
%icmp = icmp sgt i64 %a, -1
%sext = sext i1 %icmp to i8
ret i8 %sext
}
; Make sure we don't use seqz+th.ext instead of snez+addi
define i64 @sexti1_i64_setcc_2(i64 %a, i64 %b) {
; CHECK-LABEL: sexti1_i64_setcc_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%icmp = icmp eq i64 %a, %b
%sext = sext i1 %icmp to i64
ret i64 %sext
}
; Make sure we don't use th.ext instead of neg.
define i64 @sexti1_i64_setcc_3(i64 %a, i64 %b) {
; CHECK-LABEL: sexti1_i64_setcc_3:
; CHECK: # %bb.0:
; CHECK-NEXT: slt a0, a0, a1
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%icmp = icmp slt i64 %a, %b
%sext = sext i1 %icmp to i64
ret i64 %sext
}
define signext i32 @sextb_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sextb_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: sextb_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.ext a0, a0, 7, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: sextb_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: sext.b a0, a0
; RV64XTHEADBB-B-NEXT: ret
%shl = shl i32 %a, 24
%shr = ashr exact i32 %shl, 24
ret i32 %shr
}
define i64 @sextb_i64(i64 %a) nounwind {
; RV64I-LABEL: sextb_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: sextb_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.ext a0, a0, 7, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: sextb_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: sext.b a0, a0
; RV64XTHEADBB-B-NEXT: ret
%shl = shl i64 %a, 56
%shr = ashr exact i64 %shl, 56
ret i64 %shr
}
define signext i32 @sexth_i32(i32 signext %a) nounwind {
; RV64I-LABEL: sexth_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: sexth_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.ext a0, a0, 15, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: sexth_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: sext.h a0, a0
; RV64XTHEADBB-B-NEXT: ret
%shl = shl i32 %a, 16
%shr = ashr exact i32 %shl, 16
ret i32 %shr
}
define signext i32 @no_sexth_i32(i32 signext %a) nounwind {
; CHECK-LABEL: no_sexth_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a0, a0, 49
; CHECK-NEXT: srai a0, a0, 48
; CHECK-NEXT: ret
%shl = shl i32 %a, 17
%shr = ashr exact i32 %shl, 16
ret i32 %shr
}
define i64 @sexth_i64(i64 %a) nounwind {
; RV64I-LABEL: sexth_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: sexth_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.ext a0, a0, 15, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: sexth_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: sext.h a0, a0
; RV64XTHEADBB-B-NEXT: ret
%shl = shl i64 %a, 48
%shr = ashr exact i64 %shl, 48
ret i64 %shr
}
define i64 @no_sexth_i64(i64 %a) nounwind {
; CHECK-LABEL: no_sexth_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a0, a0, 49
; CHECK-NEXT: srai a0, a0, 48
; CHECK-NEXT: ret
%shl = shl i64 %a, 49
%shr = ashr exact i64 %shl, 48
ret i64 %shr
}
define i32 @zexth_i32(i32 %a) nounwind {
; RV64I-LABEL: zexth_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: zexth_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 15, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: zexth_i32:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: zext.h a0, a0
; RV64XTHEADBB-B-NEXT: ret
%and = and i32 %a, 65535
ret i32 %and
}
define i64 @zexth_i64(i64 %a) nounwind {
; RV64I-LABEL: zexth_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: zexth_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 15, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: zexth_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: zext.h a0, a0
; RV64XTHEADBB-B-NEXT: ret
%and = and i64 %a, 65535
ret i64 %and
}
define i64 @zextw_i64(i64 %a) nounwind {
; RV64I-LABEL: zextw_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: zextw_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: zextw_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: zext.w a0, a0
; RV64XTHEADBB-B-NEXT: ret
%and = and i64 %a, 4294967295
ret i64 %and
}
define i64 @zext_bf_i64(i64 %a) nounwind {
; RV64I-LABEL: zext_bf_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 47
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: zext_bf_i64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.extu a0, a0, 16, 1
; RV64XTHEADBB-NEXT: ret
%1 = lshr i64 %a, 1
%and = and i64 %1, 65535
ret i64 %and
}
define i64 @zext_bf2_i64(i64 %a) nounwind {
; RV64I-LABEL: zext_bf2_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 49
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: zext_bf2_i64:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.extu a0, a0, 15, 1
; RV64XTHEADBB-NEXT: ret
%t0 = and i64 %a, 65535
%result = lshr i64 %t0, 1
ret i64 %result
}
define i64 @zext_i64_srliw(i64 %a) nounwind {
; CHECK-LABEL: zext_i64_srliw:
; CHECK: # %bb.0:
; CHECK-NEXT: srliw a0, a0, 16
; CHECK-NEXT: ret
%1 = lshr i64 %a, 16
%and = and i64 %1, 65535
ret i64 %and
}
define signext i32 @bswap_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bswap_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: bswap_i32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.revw a0, a0
; RV64XTHEADBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1
}
; Similar to bswap_i32 but the result is not sign extended.
define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {
; RV64I-LABEL: bswap_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: and a3, a0, a3
; RV64I-NEXT: or a2, a2, a4
; RV64I-NEXT: slli a3, a3, 8
; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: bswap_i32_nosext:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.revw a0, a0
; RV64XTHEADBB-NEXT: sw a0, 0(a1)
; RV64XTHEADBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a)
store i32 %1, ptr %x
ret void
}
define i64 @bswap_i64(i64 %a) {
; RV64I-LABEL: bswap_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: srliw a3, a3, 24
; RV64I-NEXT: slli a3, a3, 24
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a4, a5, a4
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-NOB-LABEL: bswap_i64:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: th.rev a0, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: bswap_i64:
; RV64XTHEADBB-B: # %bb.0:
; RV64XTHEADBB-B-NEXT: rev8 a0, a0
; RV64XTHEADBB-B-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1
}
define void @sextw_removal_ext(i32 signext %arg, i32 signext %arg1) nounwind {
; RV64I-LABEL: sextw_removal_ext:
; RV64I: # %bb.0: # %bb
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: .LBB36_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: call foo
; RV64I-NEXT: slli a0, a0, 16
; RV64I-NEXT: srai a0, a0, 32
; RV64I-NEXT: bnez a0, .LBB36_1
; RV64I-NEXT: # %bb.2: # %bb7
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sextw_removal_ext:
; RV64XTHEADBB: # %bb.0: # %bb
; RV64XTHEADBB-NEXT: addi sp, sp, -16
; RV64XTHEADBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64XTHEADBB-NEXT: sraw a0, a0, a1
; RV64XTHEADBB-NEXT: .LBB36_1: # %bb2
; RV64XTHEADBB-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XTHEADBB-NEXT: call foo
; RV64XTHEADBB-NEXT: th.ext a0, a0, 47, 16
; RV64XTHEADBB-NEXT: bnez a0, .LBB36_1
; RV64XTHEADBB-NEXT: # %bb.2: # %bb7
; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64XTHEADBB-NEXT: addi sp, sp, 16
; RV64XTHEADBB-NEXT: ret
bb:
%i = ashr i32 %arg, %arg1
br label %bb2
bb2: ; preds = %bb2, %bb
%i3 = phi i32 [ %i, %bb ], [ %i7, %bb2 ]
%i4 = tail call i64 @foo(i32 signext %i3)
%i5 = shl i64 %i4, 16
%i6 = ashr i64 %i5, 32
%i7 = trunc i64 %i6 to i32
%i8 = icmp eq i32 %i7, 0
br i1 %i8, label %bb7, label %bb2
bb7: ; preds = %bb2
ret void
}
declare i64 @foo(i32 signext)
define void @sextw_removal_extu(i32 signext %arg, i32 signext %arg1) nounwind {
; RV64I-LABEL: sextw_removal_extu:
; RV64I: # %bb.0: # %bb
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: .LBB37_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: call foo
; RV64I-NEXT: slli a0, a0, 16
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: bnez a0, .LBB37_1
; RV64I-NEXT: # %bb.2: # %bb7
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: sextw_removal_extu:
; RV64XTHEADBB: # %bb.0: # %bb
; RV64XTHEADBB-NEXT: addi sp, sp, -16
; RV64XTHEADBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64XTHEADBB-NEXT: sraw a0, a0, a1
; RV64XTHEADBB-NEXT: .LBB37_1: # %bb2
; RV64XTHEADBB-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XTHEADBB-NEXT: call foo
; RV64XTHEADBB-NEXT: th.extu a0, a0, 47, 17
; RV64XTHEADBB-NEXT: bnez a0, .LBB37_1
; RV64XTHEADBB-NEXT: # %bb.2: # %bb7
; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64XTHEADBB-NEXT: addi sp, sp, 16
; RV64XTHEADBB-NEXT: ret
bb:
%i = ashr i32 %arg, %arg1
br label %bb2
bb2: ; preds = %bb2, %bb
%i3 = phi i32 [ %i, %bb ], [ %i7, %bb2 ]
%i4 = tail call i64 @foo(i32 signext %i3)
%i5 = shl i64 %i4, 16
%i6 = lshr i64 %i5, 33
%i7 = trunc i64 %i6 to i32
%i8 = icmp eq i32 %i7, 0
br i1 %i8, label %bb7, label %bb2
bb7: ; preds = %bb2
ret void
}
define signext i32 @hasAllNBitUsers_extu(i64 %arg1, i64 %arg2, i64 %arg3) {
; RV64I-LABEL: hasAllNBitUsers_extu:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: li a3, 256
; RV64I-NEXT: .LBB38_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a0, 47
; RV64I-NEXT: srli a0, a0, 62
; RV64I-NEXT: addi a2, a2, 1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: bltu a2, a3, .LBB38_1
; RV64I-NEXT: # %bb.2: # %bb7
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: hasAllNBitUsers_extu:
; RV64XTHEADBB: # %bb.0: # %entry
; RV64XTHEADBB-NEXT: addi a2, a2, -1
; RV64XTHEADBB-NEXT: li a3, 256
; RV64XTHEADBB-NEXT: .LBB38_1: # %bb2
; RV64XTHEADBB-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XTHEADBB-NEXT: th.extu a0, a0, 16, 15
; RV64XTHEADBB-NEXT: addi a2, a2, 1
; RV64XTHEADBB-NEXT: addw a0, a0, a1
; RV64XTHEADBB-NEXT: bltu a2, a3, .LBB38_1
; RV64XTHEADBB-NEXT: # %bb.2: # %bb7
; RV64XTHEADBB-NEXT: ret
entry:
br label %bb2
bb2: ; preds = %bb2, %entry
%i1 = phi i64 [ %arg1, %entry ], [ %i5, %bb2 ]
%i2 = phi i64 [ %arg3, %entry ], [ %i3, %bb2 ]
%i3 = add i64 %i2, 1
%i4 = lshr i64 %i1, 15
%i4b = and i64 %i4, 3
%i5 = add i64 %i4b, %arg2
%i6 = icmp ugt i64 %i2, 255
br i1 %i6, label %bb7, label %bb2
bb7: ; preds = %bb2
%i7 = trunc i64 %i5 to i32
ret i32 %i7
}
define signext i32 @hasAllNBitUsers_ext(i64 %arg1, i64 %arg2, i64 %arg3) {
; RV64I-LABEL: hasAllNBitUsers_ext:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: li a3, 256
; RV64I-NEXT: .LBB39_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a0, 47
; RV64I-NEXT: srli a0, a0, 62
; RV64I-NEXT: addi a2, a2, 1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: bltu a2, a3, .LBB39_1
; RV64I-NEXT: # %bb.2: # %bb7
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: hasAllNBitUsers_ext:
; RV64XTHEADBB: # %bb.0: # %entry
; RV64XTHEADBB-NEXT: addi a2, a2, -1
; RV64XTHEADBB-NEXT: li a3, 256
; RV64XTHEADBB-NEXT: .LBB39_1: # %bb2
; RV64XTHEADBB-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XTHEADBB-NEXT: th.extu a0, a0, 16, 15
; RV64XTHEADBB-NEXT: addi a2, a2, 1
; RV64XTHEADBB-NEXT: addw a0, a0, a1
; RV64XTHEADBB-NEXT: bltu a2, a3, .LBB39_1
; RV64XTHEADBB-NEXT: # %bb.2: # %bb7
; RV64XTHEADBB-NEXT: ret
entry:
br label %bb2
bb2: ; preds = %bb2, %entry
%i1 = phi i64 [ %arg1, %entry ], [ %i5, %bb2 ]
%i2 = phi i64 [ %arg3, %entry ], [ %i3, %bb2 ]
%i3 = add i64 %i2, 1
%i4 = ashr i64 %i1, 15
%i4b = and i64 %i4, 3
%i5 = add i64 %i4b, %arg2
%i6 = icmp ugt i64 %i2, 255
br i1 %i6, label %bb7, label %bb2
bb7: ; preds = %bb2
%i7 = trunc i64 %i5 to i32
ret i32 %i7
}
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