derek.holloway
7502bf64a4
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222 lines
8.1 KiB
LLVM
222 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define void @v4xi8_concat_vector_insert_idx0(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
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; CHECK-NEXT: vmv.s.x v8, a2
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 0
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi8_concat_vector_insert_idx1(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vmv.s.x v10, a2
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; CHECK-NEXT: vslideup.vi v8, v10, 1
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 2
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 1
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi8_concat_vector_insert_idx2(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a1)
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; CHECK-NEXT: vle8.v v9, (a0)
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
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; CHECK-NEXT: vmv.s.x v8, a2
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v9, v8, 2
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; CHECK-NEXT: vse8.v v9, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 2
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi8_concat_vector_insert_idx3(ptr %a, ptr %b, i8 %x) {
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; CHECK-LABEL: v4xi8_concat_vector_insert_idx3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a1)
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; CHECK-NEXT: vle8.v v9, (a0)
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; CHECK-NEXT: vmv.s.x v10, a2
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; CHECK-NEXT: vslideup.vi v8, v10, 1
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v9, v8, 2
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; CHECK-NEXT: vse8.v v9, (a0)
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; CHECK-NEXT: ret
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%v1 = load <2 x i8>, ptr %a
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%v2 = load <2 x i8>, ptr %b
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%concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i8> %concat, i8 %x, i32 3
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store <4 x i8> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx0(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx0:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: vle64.v v10, (a1)
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; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, ma
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx0:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: vle64.v v10, (a1)
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; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
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; RV64-NEXT: vmv.s.x v8, a2
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 0
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store <4 x i64> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx1(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: vle64.v v10, (a1)
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; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; RV32-NEXT: vslide1down.vx v9, v8, a2
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; RV32-NEXT: vslide1down.vx v9, v9, a3
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vslideup.vi v8, v9, 1
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: vle64.v v10, (a1)
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; RV64-NEXT: vmv.s.x v9, a2
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; RV64-NEXT: vslideup.vi v8, v9, 1
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 1
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store <4 x i64> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx2(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx2:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a1)
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; RV32-NEXT: vle64.v v10, (a0)
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; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, ma
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v10, v8, 2
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; RV32-NEXT: vse64.v v10, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx2:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a1)
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; RV64-NEXT: vle64.v v10, (a0)
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; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
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; RV64-NEXT: vmv.s.x v8, a2
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v10, v8, 2
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; RV64-NEXT: vse64.v v10, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 2
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store <4 x i64> %ins, ptr %a
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ret void
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}
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define void @v4xi64_concat_vector_insert_idx3(ptr %a, ptr %b, i64 %x) {
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; RV32-LABEL: v4xi64_concat_vector_insert_idx3:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a1)
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; RV32-NEXT: vle64.v v10, (a0)
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; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; RV32-NEXT: vslide1down.vx v9, v8, a2
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; RV32-NEXT: vslide1down.vx v9, v9, a3
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vslideup.vi v8, v9, 1
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v10, v8, 2
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; RV32-NEXT: vse64.v v10, (a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4xi64_concat_vector_insert_idx3:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a1)
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; RV64-NEXT: vle64.v v10, (a0)
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; RV64-NEXT: vmv.s.x v9, a2
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; RV64-NEXT: vslideup.vi v8, v9, 1
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslideup.vi v10, v8, 2
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; RV64-NEXT: vse64.v v10, (a0)
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; RV64-NEXT: ret
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%v1 = load <2 x i64>, ptr %a
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%v2 = load <2 x i64>, ptr %b
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%concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%ins = insertelement <4 x i64> %concat, i64 %x, i32 3
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store <4 x i64> %ins, ptr %a
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ret void
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}
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