derek.holloway
7502bf64a4
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700 lines
27 KiB
YAML
700 lines
27 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=liveintervals,riscv-insert-vsetvli \
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# RUN: -verify-machineinstrs | FileCheck %s
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--- |
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source_filename = "vsetvli-insert.ll"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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define <vscale x 1 x i64> @add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
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ret <vscale x 1 x i64> %a
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}
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define <vscale x 1 x i64> @load_add(ptr %0, <vscale x 1 x i64> %1, i64 %2) #0 {
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, ptr %0, i64 %2)
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%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
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ret <vscale x 1 x i64> %b
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}
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define <vscale x 1 x i64> @load_zext(ptr %0, i64 %1) #0 {
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entry:
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%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, ptr %0, i64 %1)
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%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %1)
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ret <vscale x 1 x i64> %b
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}
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define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 {
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entry:
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%a = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %0)
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ret i64 %a
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}
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define void @add_v2i64(ptr %x, ptr %y) #0 {
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%a = load <2 x i64>, ptr %x, align 16
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%b = load <2 x i64>, ptr %y, align 16
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%c = add <2 x i64> %a, %b
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store <2 x i64> %c, ptr %x, align 16
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ret void
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}
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define i64 @vreduce_add_v2i64(ptr %x) #0 {
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%v = load <2 x i64>, ptr %x, align 16
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%red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)
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ret i64 %red
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}
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define <vscale x 1 x i64> @vsetvli_add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
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entry:
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%a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)
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%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %a)
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ret <vscale x 1 x i64> %b
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}
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define <vscale x 1 x i64> @load_add_inlineasm(ptr %0, <vscale x 1 x i64> %1, i64 %2) #0 {
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, ptr %0, i64 %2)
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call void asm sideeffect "", ""()
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%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
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ret <vscale x 1 x i64> %b
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}
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define void @vmv_v_i_different_lmuls() {
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ret void
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}
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define void @pre_same_sewlmul_ratio() {
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ret void
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}
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define void @postpass_modify_vl() {
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ret void
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}
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define void @coalesce_dead_avl_addi() {
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ret void
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}
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define void @coalesce_dead_avl_nonvolatile_load() {
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ret void
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}
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define void @coalesce_dead_avl_volatile_load() {
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ret void
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}
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define void @coalesce_shrink_removed_vsetvlis_uses() {
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ret void
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}
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define void @coalesce_vl_avl_same_reg() {
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ret void
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}
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define void @coalesce_vl_clobber() {
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ret void
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}
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define void @vsetvli_vleff() {
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ret void
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}
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define void @non_li_addi() {
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ret void
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}
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attributes #0 = { "target-features"="+v" }
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...
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---
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name: add
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vr }
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- { id: 1, class: vr }
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- { id: 2, class: gprnox0 }
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- { id: 3, class: vr }
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liveins:
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- { reg: '$v8', virtual-reg: '%0' }
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- { reg: '$v9', virtual-reg: '%1' }
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- { reg: '$x10', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $v8, $v9, $x10
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; CHECK-LABEL: name: add
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; CHECK: liveins: $v8, $v9, $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype
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; CHECK-NEXT: PseudoRET implicit $v8
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%2:gprnox0 = COPY $x10
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%1:vr = COPY $v9
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%0:vr = COPY $v8
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%3:vr = PseudoVADD_VV_M1 undef $noreg, %0, %1, %2, 6, 0
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$v8 = COPY %3
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PseudoRET implicit $v8
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...
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---
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name: load_add
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: vr }
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- { id: 2, class: gprnox0 }
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- { id: 3, class: vr }
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- { id: 4, class: vr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$v8', virtual-reg: '%1' }
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- { reg: '$x11', virtual-reg: '%2' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x10, $v8, $x11
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; CHECK-LABEL: name: load_add
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; CHECK: liveins: $x10, $v8, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype
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; CHECK-NEXT: PseudoRET implicit $v8
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%2:gprnox0 = COPY $x11
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%1:vr = COPY $v8
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%0:gpr = COPY $x10
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%3:vr = PseudoVLE64_V_M1 undef $noreg, %0, %2, 6, 0
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%4:vr = PseudoVADD_VV_M1 undef $noreg, killed %3, %1, %2, 6, 0
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$v8 = COPY %4
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PseudoRET implicit $v8
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...
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---
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name: load_zext
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gprnox0 }
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- { id: 2, class: vr }
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- { id: 3, class: vr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; CHECK-LABEL: name: load_zext
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; CHECK: liveins: $x10, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY1]], $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: $v8 = COPY %3, implicit $vtype
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; CHECK-NEXT: PseudoRET implicit $v8
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%1:gprnox0 = COPY $x11
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%0:gpr = COPY $x10
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%2:vr = PseudoVLE32_V_MF2 undef $noreg, %0, %1, 5, 0
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early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, killed %2, %1, 6, 0
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$v8 = COPY %3
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PseudoRET implicit $v8
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...
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---
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name: vmv_x_s
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vr }
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- { id: 1, class: gpr }
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liveins:
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- { reg: '$v8', virtual-reg: '%0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $v8
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; CHECK-LABEL: name: vmv_x_s
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; CHECK: liveins: $v8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[COPY]], 6 /* e64 */, implicit $vtype
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; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:vr = COPY $v8
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%1:gpr = PseudoVMV_X_S %0, 6
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$x10 = COPY %1
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PseudoRET implicit $x10
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...
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---
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name: add_v2i64
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: vr }
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- { id: 3, class: vr }
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- { id: 4, class: vr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $x10, $x11
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; CHECK-LABEL: name: add_v2i64
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; CHECK: liveins: $x10, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
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; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y)
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; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoVSE64_V_M1 [[PseudoVADD_VV_M1_]], [[COPY1]], 2 /* vl */, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x)
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; CHECK-NEXT: PseudoRET
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%2:vr = PseudoVLE64_V_M1 undef $noreg, %0, 2, 6, 0 :: (load (s128) from %ir.x)
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%3:vr = PseudoVLE64_V_M1 undef $noreg, %1, 2, 6, 0 :: (load (s128) from %ir.y)
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%4:vr = PseudoVADD_VV_M1 undef $noreg, killed %2, killed %3, 2, 6, 0
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PseudoVSE64_V_M1 killed %4, %0, 2, 6 :: (store (s128) into %ir.x)
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PseudoRET
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...
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---
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name: vreduce_add_v2i64
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: vr }
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- { id: 2, class: vr }
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- { id: 3, class: vr }
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- { id: 4, class: vr }
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- { id: 5, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $x10
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; CHECK-LABEL: name: vreduce_add_v2i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
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; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVMV_V_I_M1_]], 2 /* vl */, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype
|
|
; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]
|
|
; CHECK-NEXT: PseudoRET implicit $x10
|
|
%0:gpr = COPY $x10
|
|
%1:vr = PseudoVLE64_V_M1 undef $noreg, %0, 2, 6, 0 :: (load (s128) from %ir.x)
|
|
%2:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1, 6, 0
|
|
%3:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, killed %1, killed %2, 2, 6, 1
|
|
%5:gpr = PseudoVMV_X_S killed %3, 6
|
|
$x10 = COPY %5
|
|
PseudoRET implicit $x10
|
|
|
|
...
|
|
---
|
|
name: vsetvli_add
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: vr }
|
|
- { id: 1, class: vr }
|
|
- { id: 2, class: gprnox0 }
|
|
- { id: 3, class: gprnox0 }
|
|
- { id: 4, class: vr }
|
|
liveins:
|
|
- { reg: '$v8', virtual-reg: '%0' }
|
|
- { reg: '$v9', virtual-reg: '%1' }
|
|
- { reg: '$x10', virtual-reg: '%2' }
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $v8, $v9, $x10
|
|
|
|
; CHECK-LABEL: name: vsetvli_add
|
|
; CHECK: liveins: $v8, $v9, $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
|
|
; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype
|
|
; CHECK-NEXT: PseudoRET implicit $v8
|
|
%2:gprnox0 = COPY $x10
|
|
%1:vr = COPY $v9
|
|
%0:vr = COPY $v8
|
|
%3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype
|
|
%4:vr = PseudoVADD_VV_M1 undef $noreg, %0, %1, killed %3, 6, 0
|
|
$v8 = COPY %4
|
|
PseudoRET implicit $v8
|
|
|
|
...
|
|
---
|
|
name: load_add_inlineasm
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: vr }
|
|
- { id: 2, class: gprnox0 }
|
|
- { id: 3, class: vr }
|
|
- { id: 4, class: vr }
|
|
liveins:
|
|
- { reg: '$x10', virtual-reg: '%0' }
|
|
- { reg: '$v8', virtual-reg: '%1' }
|
|
- { reg: '$x11', virtual-reg: '%2' }
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $v8, $x11
|
|
|
|
; CHECK-LABEL: name: load_add_inlineasm
|
|
; CHECK: liveins: $x10, $v8, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype
|
|
; CHECK-NEXT: PseudoRET implicit $v8
|
|
%2:gprnox0 = COPY $x11
|
|
%1:vr = COPY $v8
|
|
%0:gpr = COPY $x10
|
|
%3:vr = PseudoVLE64_V_M1 undef $noreg, %0, %2, 6, 0
|
|
INLINEASM &"", sideeffect attdialect
|
|
%4:vr = PseudoVADD_VV_M1 undef $noreg, killed %3, %1, %2, 6, 0
|
|
$v8 = COPY %4
|
|
PseudoRET implicit $v8
|
|
|
|
...
|
|
---
|
|
name: vmv_v_i_different_lmuls
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x10, $v8, $x11
|
|
|
|
; CHECK-LABEL: name: vmv_v_i_different_lmuls
|
|
; CHECK: liveins: $x10, $v8, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 undef $noreg, 4 /* vl */, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6, 3
|
|
%4:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3, 0
|
|
PseudoRET
|
|
...
|
|
---
|
|
# make sure we don't try to perform PRE when one of the blocks is sew/lmul ratio
|
|
# only
|
|
name: pre_same_sewlmul_ratio
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; CHECK-LABEL: name: pre_same_sewlmul_ratio
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; CHECK-NEXT: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %cond:gpr = COPY $x10
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: BEQ %cond, $x0, %bb.2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.2(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: BEQ %cond, $x0, %bb.4
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3:
|
|
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: PseudoCALL $noreg, csr_ilp32_lp64
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.4:
|
|
; CHECK-NEXT: $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S undef $noreg, 5 /* e32 */, implicit $vtype
|
|
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
bb.0:
|
|
liveins: $x10
|
|
%cond:gpr = COPY $x10
|
|
%1:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5, 0
|
|
BEQ %cond, $x0, %bb.2
|
|
bb.1:
|
|
%2:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2, 6, 0
|
|
bb.2: ; the exit info here should have sew/lmul ratio only
|
|
BEQ %cond, $x0, %bb.4
|
|
bb.3:
|
|
PseudoCALL $noreg, csr_ilp32_lp64
|
|
bb.4: ; this block will have PRE attempted on it
|
|
%4:gpr = PseudoVMV_X_S undef $noreg, 5
|
|
%5:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5, 0
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: postpass_modify_vl
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x1
|
|
; CHECK-LABEL: name: postpass_modify_vl
|
|
; CHECK: liveins: $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $vtype
|
|
; CHECK-NEXT: $vl = COPY $x1
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
|
|
%1:gpr = COPY $vtype
|
|
$vl = COPY $x1
|
|
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
|
|
%4:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3, 6, 0
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: coalesce_dead_avl_addi
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
; CHECK-LABEL: name: coalesce_dead_avl_addi
|
|
; CHECK: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
|
|
; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
%avl:gprnox0 = ADDI $x0, 42
|
|
dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype
|
|
%x:gpr = PseudoVMV_X_S $noreg, 6
|
|
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
|
|
$v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: coalesce_dead_avl_nonvolatile_load
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x1
|
|
; CHECK-LABEL: name: coalesce_dead_avl_nonvolatile_load
|
|
; CHECK: liveins: $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %ptr:gpr = COPY $x1
|
|
; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (dereferenceable load (s32))
|
|
; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
|
|
; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
%ptr:gpr = COPY $x1
|
|
%avl:gprnox0 = LW killed %ptr, 0 :: (dereferenceable load (s32))
|
|
dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype
|
|
%x:gpr = PseudoVMV_X_S $noreg, 6
|
|
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
|
|
$v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: coalesce_dead_avl_volatile_load
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x1
|
|
; CHECK-LABEL: name: coalesce_dead_avl_volatile_load
|
|
; CHECK: liveins: $x1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %ptr:gpr = COPY $x1
|
|
; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (volatile dereferenceable load (s32))
|
|
; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
|
|
; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
%ptr:gpr = COPY $x1
|
|
%avl:gprnox0 = LW killed %ptr, 0 :: (volatile dereferenceable load (s32))
|
|
dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype
|
|
%x:gpr = PseudoVMV_X_S $noreg, 6
|
|
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
|
|
$v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: coalesce_shrink_removed_vsetvlis_uses
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x10, $v8
|
|
; CHECK-LABEL: name: coalesce_shrink_removed_vsetvlis_uses
|
|
; CHECK: liveins: $x10, $v8
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %avl2:gprnox0 = ADDI $x0, 2
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLI %avl2, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: %x:gpr = COPY $x10
|
|
; CHECK-NEXT: renamable $v8 = PseudoVMV_S_X undef renamable $v8, %x, 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET implicit $v8
|
|
%avl1:gprnox0 = ADDI $x0, 1
|
|
dead $x0 = PseudoVSETVLI %avl1:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype
|
|
%avl2:gprnox0 = ADDI $x0, 2
|
|
dead $x0 = PseudoVSETVLI %avl2:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype
|
|
%x:gpr = COPY $x10
|
|
renamable $v8 = PseudoVMV_S_X undef renamable $v8, killed renamable %x, 1, 5
|
|
PseudoRET implicit $v8
|
|
...
|
|
---
|
|
name: coalesce_vl_avl_same_reg
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x8, $v8
|
|
; CHECK-LABEL: name: coalesce_vl_avl_same_reg
|
|
; CHECK: liveins: $x8, $v8
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %x:gprnox0 = COPY $x8
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype
|
|
; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
%x:gprnox0 = COPY $x8
|
|
dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
|
|
%v:vr = COPY $v8, implicit $vtype
|
|
%x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
|
|
...
|
|
---
|
|
# Because of the %y:gprnox0 = COPY %x, we can't extend the live range of %x from
|
|
# the second vsetvli to the first vsetvli when coalescing.
|
|
name: coalesce_vl_clobber
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x8, $v8
|
|
; CHECK-LABEL: name: coalesce_vl_clobber
|
|
; CHECK: liveins: $x8, $v8
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %x:gprnox0 = COPY $x8
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: dead %y:gprnox0 = COPY %x
|
|
; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype
|
|
; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
%x:gprnox0 = COPY $x8
|
|
dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
|
|
%y:gprnox0 = COPY %x
|
|
%v:vr = COPY $v8, implicit $vtype
|
|
%x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
|
|
...
|
|
---
|
|
name: vsetvli_vleff
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; CHECK-LABEL: name: vsetvli_vleff
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %vl:gpr = COPY $x0
|
|
; CHECK-NEXT: BNE $x0, $x0, %bb.2
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.2(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: $noreg, $x0 = PseudoVLE16FF_V_M1 $noreg, $noreg, 0 /* vl */, 4 /* e16 */, 2 /* tu, ma */, implicit $vl, implicit $vtype, implicit-def $vl
|
|
; CHECK-NEXT: %vl:gpr = PseudoReadVL implicit $vl
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: $x10 = COPY %vl
|
|
; CHECK-NEXT: PseudoRET implicit killed $x10
|
|
bb.0:
|
|
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
|
|
%vl:gpr = COPY $x0
|
|
BNE $x0, $x0, %bb.2
|
|
PseudoBR %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.2(0x80000000)
|
|
|
|
$noreg, %vl:gpr = PseudoVLE16FF_V_M1 $noreg, $noreg, 0, 4 /* e16 */, 2 /* tu, ma */
|
|
|
|
bb.2:
|
|
$x10 = COPY %vl
|
|
PseudoRET implicit killed $x10
|
|
...
|
|
---
|
|
# The two vsetvlis will be coalesced so the ADDI will be made dead and removed.
|
|
# Make sure we shrink the live interval of %0.
|
|
name: non_li_addi
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $x10
|
|
; CHECK-LABEL: name: non_li_addi
|
|
; CHECK: liveins: $x10
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: dead [[PseudoVSETIVLI:%[0-9]+]]:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
%0:gpr = COPY $x10
|
|
%1:gprnox0 = ADDI %0, 1
|
|
%2:gprnox0 = PseudoVSETVLI %1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
%3:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
PseudoRET
|