derek.holloway
7502bf64a4
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76 lines
3.2 KiB
LLVM
76 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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define <vscale x 8 x i64> @vwsub_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
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; CHECK-LABEL: vwsub_wv_mask_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv4r.v v24, v8
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; CHECK-NEXT: li a0, 42
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; CHECK-NEXT: vmslt.vx v0, v8, a0
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; CHECK-NEXT: vmv8r.v v8, v16
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
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; CHECK-NEXT: vwsub.wv v8, v8, v24, v0.t
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; CHECK-NEXT: ret
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%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
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%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
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%sa = sext <vscale x 8 x i32> %a to <vscale x 8 x i64>
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%ret = sub <vscale x 8 x i64> %y, %sa
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ret <vscale x 8 x i64> %ret
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}
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define <vscale x 8 x i64> @vwsubu_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
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; CHECK-LABEL: vwsubu_wv_mask_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv4r.v v24, v8
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; CHECK-NEXT: li a0, 42
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; CHECK-NEXT: vmslt.vx v0, v8, a0
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; CHECK-NEXT: vmv8r.v v8, v16
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
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; CHECK-NEXT: vwsubu.wv v8, v8, v24, v0.t
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; CHECK-NEXT: ret
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%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
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%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
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%sa = zext <vscale x 8 x i32> %a to <vscale x 8 x i64>
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%ret = sub <vscale x 8 x i64> %y, %sa
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ret <vscale x 8 x i64> %ret
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}
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define <vscale x 8 x i64> @vwsubu_vv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {
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; CHECK-LABEL: vwsubu_vv_mask_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv4r.v v16, v12
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; CHECK-NEXT: li a0, 42
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; CHECK-NEXT: vmslt.vx v0, v8, a0
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; CHECK-NEXT: vmv.v.i v12, 0
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; CHECK-NEXT: vmerge.vvm v20, v12, v8, v0
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; CHECK-NEXT: vwsubu.vv v8, v16, v20
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; CHECK-NEXT: ret
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%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
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%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
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%sa = zext <vscale x 8 x i32> %a to <vscale x 8 x i64>
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%sy = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>
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%ret = sub <vscale x 8 x i64> %sy, %sa
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ret <vscale x 8 x i64> %ret
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}
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define <vscale x 8 x i64> @vwsub_wv_mask_v8i32_nonzero(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
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; CHECK-LABEL: vwsub_wv_mask_v8i32_nonzero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 42
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; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmslt.vx v0, v8, a0
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; CHECK-NEXT: vmv.v.i v12, 1
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; CHECK-NEXT: vmerge.vvm v24, v12, v8, v0
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; CHECK-NEXT: vwsub.wv v8, v16, v24
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; CHECK-NEXT: ret
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%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
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%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> splat (i32 1)
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%sa = sext <vscale x 8 x i32> %a to <vscale x 8 x i64>
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%ret = sub <vscale x 8 x i64> %y, %sa
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ret <vscale x 8 x i64> %ret
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}
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