derek.holloway
7502bf64a4
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494 lines
17 KiB
LLVM
494 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+short-forward-branch-iload,+short-forward-branch-imm < %s \
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; RUN: | FileCheck -check-prefix=RV32I-WITH-SFB %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqci,+short-forward-branch-iload,+short-forward-branch-imm < %s \
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; RUN: | FileCheck -check-prefix=XQCI-WITH-SFB %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+short-forward-branch-iload,+short-forward-branch-imm < %s \
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; RUN: | FileCheck -check-prefix=RV64I-WITH-SFB %s
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@ga = global [16 x i8] zeroinitializer, align 8
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;; This tests that we can fold offsets into the SFB Load Pseudos.
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define i64 @load_cond_ga_dword(i64 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_dword:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a4, %hi(ga)
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; RV32I-WITH-SFB-NEXT: addi a4, a4, %lo(ga)
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; RV32I-WITH-SFB-NEXT: bne a2, a3, .LBB0_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: lw a0, 8(a4)
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; RV32I-WITH-SFB-NEXT: .LBB0_2:
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; RV32I-WITH-SFB-NEXT: bne a2, a3, .LBB0_4
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; RV32I-WITH-SFB-NEXT: # %bb.3:
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; RV32I-WITH-SFB-NEXT: lw a1, 12(a4)
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; RV32I-WITH-SFB-NEXT: .LBB0_4:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_dword:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a4, ga
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; XQCI-WITH-SFB-NEXT: bne a2, a3, .LBB0_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: lw a0, 8(a4)
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; XQCI-WITH-SFB-NEXT: .LBB0_2:
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; XQCI-WITH-SFB-NEXT: bne a2, a3, .LBB0_4
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; XQCI-WITH-SFB-NEXT: # %bb.3:
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; XQCI-WITH-SFB-NEXT: lw a1, 12(a4)
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; XQCI-WITH-SFB-NEXT: .LBB0_4:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_dword:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga+8)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB0_2
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; RV64I-WITH-SFB-NEXT: # %bb.1:
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; RV64I-WITH-SFB-NEXT: ld a0, %lo(ga+8)(a3)
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; RV64I-WITH-SFB-NEXT: .LBB0_2:
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; RV64I-WITH-SFB-NEXT: ret
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%addr = getelementptr i8, ptr @ga, i32 8
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%val = load i64, ptr %addr, align 8
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%cmp = icmp eq i32 %b, %c
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%cmv = select i1 %cmp, i64 %val, i64 %a
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ret i64 %cmv
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}
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define i64 @load_cond_ga_word_sext(i64 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_word_sext:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a4, %hi(ga+12)
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; RV32I-WITH-SFB-NEXT: lw a4, %lo(ga+12)(a4)
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; RV32I-WITH-SFB-NEXT: bne a2, a3, .LBB1_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: mv a0, a4
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; RV32I-WITH-SFB-NEXT: .LBB1_2:
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; RV32I-WITH-SFB-NEXT: bne a2, a3, .LBB1_4
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; RV32I-WITH-SFB-NEXT: # %bb.3:
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; RV32I-WITH-SFB-NEXT: srai a1, a4, 31
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; RV32I-WITH-SFB-NEXT: .LBB1_4:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_word_sext:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a4, ga+12
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; XQCI-WITH-SFB-NEXT: lw a4, 0(a4)
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; XQCI-WITH-SFB-NEXT: qc.mveq a0, a2, a3, a4
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; XQCI-WITH-SFB-NEXT: bne a2, a3, .LBB1_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: srai a1, a4, 31
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; XQCI-WITH-SFB-NEXT: .LBB1_2:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_word_sext:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga+12)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB1_2
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; RV64I-WITH-SFB-NEXT: # %bb.1:
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; RV64I-WITH-SFB-NEXT: lw a0, %lo(ga+12)(a3)
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; RV64I-WITH-SFB-NEXT: .LBB1_2:
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; RV64I-WITH-SFB-NEXT: ret
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%addr = getelementptr i8, ptr @ga, i32 12
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%val = load i32, ptr %addr, align 4
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%ext = sext i32 %val to i64
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%cmp = icmp eq i32 %b, %c
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%cmv = select i1 %cmp, i64 %ext, i64 %a
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ret i64 %cmv
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}
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define i64 @load_cond_ga_word_zext(i64 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_word_zext:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a4, %hi(ga+12)
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; RV32I-WITH-SFB-NEXT: bne a2, a3, .LBB2_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: lw a0, %lo(ga+12)(a4)
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; RV32I-WITH-SFB-NEXT: .LBB2_2:
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; RV32I-WITH-SFB-NEXT: bne a2, a3, .LBB2_4
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; RV32I-WITH-SFB-NEXT: # %bb.3:
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; RV32I-WITH-SFB-NEXT: li a1, 0
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; RV32I-WITH-SFB-NEXT: .LBB2_4:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_word_zext:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a4, ga+12
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; XQCI-WITH-SFB-NEXT: bne a2, a3, .LBB2_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: lw a0, 0(a4)
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; XQCI-WITH-SFB-NEXT: .LBB2_2:
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; XQCI-WITH-SFB-NEXT: bne a2, a3, .LBB2_4
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; XQCI-WITH-SFB-NEXT: # %bb.3:
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; XQCI-WITH-SFB-NEXT: li a1, 0
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; XQCI-WITH-SFB-NEXT: .LBB2_4:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_word_zext:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga+12)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB2_2
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; RV64I-WITH-SFB-NEXT: # %bb.1:
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; RV64I-WITH-SFB-NEXT: lwu a0, %lo(ga+12)(a3)
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; RV64I-WITH-SFB-NEXT: .LBB2_2:
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; RV64I-WITH-SFB-NEXT: ret
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%addr = getelementptr i8, ptr @ga, i32 12
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%val = load i32, ptr %addr, align 4
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%ext = zext i32 %val to i64
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%cmp = icmp eq i32 %b, %c
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%cmv = select i1 %cmp, i64 %ext, i64 %a
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ret i64 %cmv
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}
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define i32 @load_cond_ga_word(i32 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_word:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV32I-WITH-SFB-NEXT: bne a1, a2, .LBB3_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: lw a0, %lo(ga+4)(a3)
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; RV32I-WITH-SFB-NEXT: .LBB3_2:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_word:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a3, ga+4
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; XQCI-WITH-SFB-NEXT: bne a1, a2, .LBB3_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: lw a0, 0(a3)
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; XQCI-WITH-SFB-NEXT: .LBB3_2:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_word:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB3_2
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; RV64I-WITH-SFB-NEXT: # %bb.1:
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; RV64I-WITH-SFB-NEXT: lw a0, %lo(ga+4)(a3)
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; RV64I-WITH-SFB-NEXT: .LBB3_2:
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; RV64I-WITH-SFB-NEXT: ret
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%addr = getelementptr i8, ptr @ga, i32 4
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%val = load i32, ptr %addr, align 4
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%cmp = icmp eq i32 %b, %c
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%cmv = select i1 %cmp, i32 %val, i32 %a
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ret i32 %cmv
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}
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define i32 @load_cond_ga_half_sext(i32 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_half_sext:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV32I-WITH-SFB-NEXT: bne a1, a2, .LBB4_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: lh a0, %lo(ga+6)(a3)
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; RV32I-WITH-SFB-NEXT: .LBB4_2:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_half_sext:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a3, ga+6
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; XQCI-WITH-SFB-NEXT: bne a1, a2, .LBB4_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: lh a0, 0(a3)
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; XQCI-WITH-SFB-NEXT: .LBB4_2:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_half_sext:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB4_2
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; RV64I-WITH-SFB-NEXT: # %bb.1:
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; RV64I-WITH-SFB-NEXT: lh a0, %lo(ga+6)(a3)
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; RV64I-WITH-SFB-NEXT: .LBB4_2:
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; RV64I-WITH-SFB-NEXT: ret
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%addr = getelementptr i8, ptr @ga, i32 6
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%val = load i16, ptr %addr, align 2
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%ext = sext i16 %val to i32
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%cmp = icmp eq i32 %b, %c
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%cmv = select i1 %cmp, i32 %ext, i32 %a
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ret i32 %cmv
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}
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define i32 @load_cond_ga_half_zext(i32 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_half_zext:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV32I-WITH-SFB-NEXT: bne a1, a2, .LBB5_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: lhu a0, %lo(ga+6)(a3)
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; RV32I-WITH-SFB-NEXT: .LBB5_2:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_half_zext:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a3, ga+6
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; XQCI-WITH-SFB-NEXT: bne a1, a2, .LBB5_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: lhu a0, 0(a3)
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; XQCI-WITH-SFB-NEXT: .LBB5_2:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_half_zext:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB5_2
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; RV64I-WITH-SFB-NEXT: # %bb.1:
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; RV64I-WITH-SFB-NEXT: lhu a0, %lo(ga+6)(a3)
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; RV64I-WITH-SFB-NEXT: .LBB5_2:
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; RV64I-WITH-SFB-NEXT: ret
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%addr = getelementptr i8, ptr @ga, i32 6
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%val = load i16, ptr %addr, align 2
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%ext = zext i16 %val to i32
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%cmp = icmp eq i32 %b, %c
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%cmv = select i1 %cmp, i32 %ext, i32 %a
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ret i32 %cmv
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}
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define i32 @load_cond_ga_byte_sext(i32 %a, i32 %b, i32 %c) {
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; RV32I-WITH-SFB-LABEL: load_cond_ga_byte_sext:
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; RV32I-WITH-SFB: # %bb.0:
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; RV32I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV32I-WITH-SFB-NEXT: bne a1, a2, .LBB6_2
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; RV32I-WITH-SFB-NEXT: # %bb.1:
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; RV32I-WITH-SFB-NEXT: lb a0, %lo(ga+7)(a3)
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; RV32I-WITH-SFB-NEXT: .LBB6_2:
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; RV32I-WITH-SFB-NEXT: ret
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;
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; XQCI-WITH-SFB-LABEL: load_cond_ga_byte_sext:
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; XQCI-WITH-SFB: # %bb.0:
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; XQCI-WITH-SFB-NEXT: qc.e.li a3, ga+7
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; XQCI-WITH-SFB-NEXT: bne a1, a2, .LBB6_2
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; XQCI-WITH-SFB-NEXT: # %bb.1:
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; XQCI-WITH-SFB-NEXT: lb a0, 0(a3)
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; XQCI-WITH-SFB-NEXT: .LBB6_2:
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; XQCI-WITH-SFB-NEXT: ret
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;
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; RV64I-WITH-SFB-LABEL: load_cond_ga_byte_sext:
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; RV64I-WITH-SFB: # %bb.0:
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; RV64I-WITH-SFB-NEXT: sext.w a2, a2
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; RV64I-WITH-SFB-NEXT: sext.w a1, a1
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; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga)
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; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB6_2
|
|
; RV64I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV64I-WITH-SFB-NEXT: lb a0, %lo(ga+7)(a3)
|
|
; RV64I-WITH-SFB-NEXT: .LBB6_2:
|
|
; RV64I-WITH-SFB-NEXT: ret
|
|
%addr = getelementptr i8, ptr @ga, i32 7
|
|
%val = load i8, ptr %addr, align 1
|
|
%ext = sext i8 %val to i32
|
|
%cmp = icmp eq i32 %b, %c
|
|
%cmv = select i1 %cmp, i32 %ext, i32 %a
|
|
ret i32 %cmv
|
|
}
|
|
|
|
define i32 @load_cond_ga_byte_zext(i32 %a, i32 %b, i32 %c) {
|
|
; RV32I-WITH-SFB-LABEL: load_cond_ga_byte_zext:
|
|
; RV32I-WITH-SFB: # %bb.0:
|
|
; RV32I-WITH-SFB-NEXT: lui a3, %hi(ga)
|
|
; RV32I-WITH-SFB-NEXT: bne a1, a2, .LBB7_2
|
|
; RV32I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV32I-WITH-SFB-NEXT: lbu a0, %lo(ga+7)(a3)
|
|
; RV32I-WITH-SFB-NEXT: .LBB7_2:
|
|
; RV32I-WITH-SFB-NEXT: ret
|
|
;
|
|
; XQCI-WITH-SFB-LABEL: load_cond_ga_byte_zext:
|
|
; XQCI-WITH-SFB: # %bb.0:
|
|
; XQCI-WITH-SFB-NEXT: qc.e.li a3, ga+7
|
|
; XQCI-WITH-SFB-NEXT: bne a1, a2, .LBB7_2
|
|
; XQCI-WITH-SFB-NEXT: # %bb.1:
|
|
; XQCI-WITH-SFB-NEXT: lbu a0, 0(a3)
|
|
; XQCI-WITH-SFB-NEXT: .LBB7_2:
|
|
; XQCI-WITH-SFB-NEXT: ret
|
|
;
|
|
; RV64I-WITH-SFB-LABEL: load_cond_ga_byte_zext:
|
|
; RV64I-WITH-SFB: # %bb.0:
|
|
; RV64I-WITH-SFB-NEXT: sext.w a2, a2
|
|
; RV64I-WITH-SFB-NEXT: sext.w a1, a1
|
|
; RV64I-WITH-SFB-NEXT: lui a3, %hi(ga)
|
|
; RV64I-WITH-SFB-NEXT: bne a1, a2, .LBB7_2
|
|
; RV64I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV64I-WITH-SFB-NEXT: lbu a0, %lo(ga+7)(a3)
|
|
; RV64I-WITH-SFB-NEXT: .LBB7_2:
|
|
; RV64I-WITH-SFB-NEXT: ret
|
|
%addr = getelementptr i8, ptr @ga, i32 7
|
|
%val = load i8, ptr %addr, align 1
|
|
%ext = zext i8 %val to i32
|
|
%cmp = icmp eq i32 %b, %c
|
|
%cmv = select i1 %cmp, i32 %ext, i32 %a
|
|
ret i32 %cmv
|
|
}
|
|
|
|
;; Check we handle cases where the branch is with an immediate
|
|
|
|
define i32 @load_cond_ga_word_imm(i32 %a, i32 %b) {
|
|
; RV32I-WITH-SFB-LABEL: load_cond_ga_word_imm:
|
|
; RV32I-WITH-SFB: # %bb.0:
|
|
; RV32I-WITH-SFB-NEXT: lui a2, %hi(ga)
|
|
; RV32I-WITH-SFB-NEXT: li a3, 14
|
|
; RV32I-WITH-SFB-NEXT: bne a1, a3, .LBB8_2
|
|
; RV32I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV32I-WITH-SFB-NEXT: lw a0, %lo(ga+4)(a2)
|
|
; RV32I-WITH-SFB-NEXT: .LBB8_2:
|
|
; RV32I-WITH-SFB-NEXT: ret
|
|
;
|
|
; XQCI-WITH-SFB-LABEL: load_cond_ga_word_imm:
|
|
; XQCI-WITH-SFB: # %bb.0:
|
|
; XQCI-WITH-SFB-NEXT: qc.e.li a2, ga+4
|
|
; XQCI-WITH-SFB-NEXT: qc.bnei a1, 14, .LBB8_2
|
|
; XQCI-WITH-SFB-NEXT: # %bb.1:
|
|
; XQCI-WITH-SFB-NEXT: lw a0, 0(a2)
|
|
; XQCI-WITH-SFB-NEXT: .LBB8_2:
|
|
; XQCI-WITH-SFB-NEXT: ret
|
|
;
|
|
; RV64I-WITH-SFB-LABEL: load_cond_ga_word_imm:
|
|
; RV64I-WITH-SFB: # %bb.0:
|
|
; RV64I-WITH-SFB-NEXT: sext.w a1, a1
|
|
; RV64I-WITH-SFB-NEXT: lui a2, %hi(ga)
|
|
; RV64I-WITH-SFB-NEXT: li a3, 14
|
|
; RV64I-WITH-SFB-NEXT: bne a1, a3, .LBB8_2
|
|
; RV64I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV64I-WITH-SFB-NEXT: lw a0, %lo(ga+4)(a2)
|
|
; RV64I-WITH-SFB-NEXT: .LBB8_2:
|
|
; RV64I-WITH-SFB-NEXT: ret
|
|
%addr = getelementptr i8, ptr @ga, i32 4
|
|
%val = load i32, ptr %addr, align 4
|
|
%cmp = icmp eq i32 %b, 14
|
|
%cmv = select i1 %cmp, i32 %val, i32 %a
|
|
ret i32 %cmv
|
|
}
|
|
|
|
;; Negative Tests
|
|
|
|
|
|
define i32 @load_cond_ga_word_addr_cond(i32 %a, ptr %b) {
|
|
; RV32I-WITH-SFB-LABEL: load_cond_ga_word_addr_cond:
|
|
; RV32I-WITH-SFB: # %bb.0:
|
|
; RV32I-WITH-SFB-NEXT: lui a2, %hi(ga)
|
|
; RV32I-WITH-SFB-NEXT: addi a2, a2, %lo(ga)
|
|
; RV32I-WITH-SFB-NEXT: addi a3, a2, 4
|
|
; RV32I-WITH-SFB-NEXT: beq a3, a1, .LBB9_2
|
|
; RV32I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV32I-WITH-SFB-NEXT: lw a0, 4(a2)
|
|
; RV32I-WITH-SFB-NEXT: .LBB9_2:
|
|
; RV32I-WITH-SFB-NEXT: ret
|
|
;
|
|
; XQCI-WITH-SFB-LABEL: load_cond_ga_word_addr_cond:
|
|
; XQCI-WITH-SFB: # %bb.0:
|
|
; XQCI-WITH-SFB-NEXT: qc.e.li a2, ga
|
|
; XQCI-WITH-SFB-NEXT: addi a3, a2, 4
|
|
; XQCI-WITH-SFB-NEXT: beq a3, a1, .LBB9_2
|
|
; XQCI-WITH-SFB-NEXT: # %bb.1:
|
|
; XQCI-WITH-SFB-NEXT: lw a0, 4(a2)
|
|
; XQCI-WITH-SFB-NEXT: .LBB9_2:
|
|
; XQCI-WITH-SFB-NEXT: ret
|
|
;
|
|
; RV64I-WITH-SFB-LABEL: load_cond_ga_word_addr_cond:
|
|
; RV64I-WITH-SFB: # %bb.0:
|
|
; RV64I-WITH-SFB-NEXT: lui a2, %hi(ga)
|
|
; RV64I-WITH-SFB-NEXT: addi a2, a2, %lo(ga)
|
|
; RV64I-WITH-SFB-NEXT: addi a3, a2, 4
|
|
; RV64I-WITH-SFB-NEXT: beq a3, a1, .LBB9_2
|
|
; RV64I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV64I-WITH-SFB-NEXT: lw a0, 4(a2)
|
|
; RV64I-WITH-SFB-NEXT: .LBB9_2:
|
|
; RV64I-WITH-SFB-NEXT: ret
|
|
%addr = getelementptr i8, ptr @ga, i32 4
|
|
%val = load i32, ptr %addr, align 4
|
|
%cmp = icmp ne ptr %addr, %b
|
|
%cmv = select i1 %cmp, i32 %val, i32 %a
|
|
ret i32 %cmv
|
|
}
|
|
|
|
define i32 @load_cond_ga_word_addr_cond_imm(i32 %a) {
|
|
; RV32I-WITH-SFB-LABEL: load_cond_ga_word_addr_cond_imm:
|
|
; RV32I-WITH-SFB: # %bb.0:
|
|
; RV32I-WITH-SFB-NEXT: lui a1, %hi(ga)
|
|
; RV32I-WITH-SFB-NEXT: addi a1, a1, %lo(ga)
|
|
; RV32I-WITH-SFB-NEXT: addi a2, a1, 4
|
|
; RV32I-WITH-SFB-NEXT: beqz a2, .LBB10_2
|
|
; RV32I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV32I-WITH-SFB-NEXT: lw a0, 4(a1)
|
|
; RV32I-WITH-SFB-NEXT: .LBB10_2:
|
|
; RV32I-WITH-SFB-NEXT: ret
|
|
;
|
|
; XQCI-WITH-SFB-LABEL: load_cond_ga_word_addr_cond_imm:
|
|
; XQCI-WITH-SFB: # %bb.0:
|
|
; XQCI-WITH-SFB-NEXT: qc.e.li a1, ga
|
|
; XQCI-WITH-SFB-NEXT: addi a2, a1, 4
|
|
; XQCI-WITH-SFB-NEXT: beqz a2, .LBB10_2
|
|
; XQCI-WITH-SFB-NEXT: # %bb.1:
|
|
; XQCI-WITH-SFB-NEXT: lw a0, 4(a1)
|
|
; XQCI-WITH-SFB-NEXT: .LBB10_2:
|
|
; XQCI-WITH-SFB-NEXT: ret
|
|
;
|
|
; RV64I-WITH-SFB-LABEL: load_cond_ga_word_addr_cond_imm:
|
|
; RV64I-WITH-SFB: # %bb.0:
|
|
; RV64I-WITH-SFB-NEXT: lui a1, %hi(ga)
|
|
; RV64I-WITH-SFB-NEXT: addi a1, a1, %lo(ga)
|
|
; RV64I-WITH-SFB-NEXT: addi a2, a1, 4
|
|
; RV64I-WITH-SFB-NEXT: beqz a2, .LBB10_2
|
|
; RV64I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV64I-WITH-SFB-NEXT: lw a0, 4(a1)
|
|
; RV64I-WITH-SFB-NEXT: .LBB10_2:
|
|
; RV64I-WITH-SFB-NEXT: ret
|
|
%addr = getelementptr i8, ptr @ga, i32 4
|
|
%val = load i32, ptr %addr, align 4
|
|
%cmp = icmp ne ptr %addr, null
|
|
%cmv = select i1 %cmp, i32 %val, i32 %a
|
|
ret i32 %cmv
|
|
}
|
|
|
|
define i32 @load_cond_ga_word_addr_false(i32 %a, i32 %b) {
|
|
; RV32I-WITH-SFB-LABEL: load_cond_ga_word_addr_false:
|
|
; RV32I-WITH-SFB: # %bb.0:
|
|
; RV32I-WITH-SFB-NEXT: lui a2, %hi(ga)
|
|
; RV32I-WITH-SFB-NEXT: addi a2, a2, %lo(ga)
|
|
; RV32I-WITH-SFB-NEXT: beq a0, a1, .LBB11_2
|
|
; RV32I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV32I-WITH-SFB-NEXT: lw a2, 4(a2)
|
|
; RV32I-WITH-SFB-NEXT: .LBB11_2:
|
|
; RV32I-WITH-SFB-NEXT: mv a0, a2
|
|
; RV32I-WITH-SFB-NEXT: ret
|
|
;
|
|
; XQCI-WITH-SFB-LABEL: load_cond_ga_word_addr_false:
|
|
; XQCI-WITH-SFB: # %bb.0:
|
|
; XQCI-WITH-SFB-NEXT: qc.e.li a2, ga
|
|
; XQCI-WITH-SFB-NEXT: beq a0, a1, .LBB11_2
|
|
; XQCI-WITH-SFB-NEXT: # %bb.1:
|
|
; XQCI-WITH-SFB-NEXT: lw a2, 4(a2)
|
|
; XQCI-WITH-SFB-NEXT: .LBB11_2:
|
|
; XQCI-WITH-SFB-NEXT: mv a0, a2
|
|
; XQCI-WITH-SFB-NEXT: ret
|
|
;
|
|
; RV64I-WITH-SFB-LABEL: load_cond_ga_word_addr_false:
|
|
; RV64I-WITH-SFB: # %bb.0:
|
|
; RV64I-WITH-SFB-NEXT: sext.w a1, a1
|
|
; RV64I-WITH-SFB-NEXT: sext.w a2, a0
|
|
; RV64I-WITH-SFB-NEXT: lui a0, %hi(ga)
|
|
; RV64I-WITH-SFB-NEXT: addi a0, a0, %lo(ga)
|
|
; RV64I-WITH-SFB-NEXT: beq a2, a1, .LBB11_2
|
|
; RV64I-WITH-SFB-NEXT: # %bb.1:
|
|
; RV64I-WITH-SFB-NEXT: lw a0, 4(a0)
|
|
; RV64I-WITH-SFB-NEXT: .LBB11_2:
|
|
; RV64I-WITH-SFB-NEXT: ret
|
|
%addr = getelementptr i8, ptr @ga, i32 4
|
|
%val = load i32, ptr %addr, align 4
|
|
%cmp = icmp ne i32 %a, %b
|
|
%addr_int = ptrtoint ptr @ga to i32
|
|
%cmv = select i1 %cmp, i32 %val, i32 %addr_int
|
|
ret i32 %cmv
|
|
}
|