derek.holloway
7502bf64a4
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650 lines
18 KiB
LLVM
650 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen2/i64/g' %s | sed 's/XLen/32/g' |llc -mtriple=riscv32 -mattr=+m | \
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; RUN: FileCheck %s --check-prefix=RV32
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; RUN: sed 's/iXLen2/i128/g' %s | sed 's/XLen/64/g'| llc -mtriple=riscv64 -mattr=+m | \
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; RUN: FileCheck %s --check-prefix=RV64
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define iXLen2 @test_urem_3(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_3:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 699051
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: addi a2, a2, -1365
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: mulhu a1, a0, a2
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; RV32-NEXT: srli a2, a1, 1
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; RV32-NEXT: andi a1, a1, -2
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_3:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 699051
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, -1365
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: srli a2, a1, 1
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; RV64-NEXT: andi a1, a1, -2
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 3
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_5(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_5:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 838861
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: addi a2, a2, -819
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: mulhu a1, a0, a2
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; RV32-NEXT: srli a2, a1, 2
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; RV32-NEXT: andi a1, a1, -4
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_5:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 838861
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, -819
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: srli a2, a1, 2
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; RV64-NEXT: andi a1, a1, -4
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 5
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_7(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_7:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a2, 262144
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; RV32-NEXT: slli a3, a1, 2
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; RV32-NEXT: srli a4, a0, 30
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; RV32-NEXT: srli a1, a1, 28
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; RV32-NEXT: or a3, a4, a3
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; RV32-NEXT: lui a4, 149797
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; RV32-NEXT: addi a2, a2, -1
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; RV32-NEXT: and a0, a0, a2
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; RV32-NEXT: and a2, a3, a2
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; RV32-NEXT: add a0, a0, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: addi a1, a4, -1755
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: sub a2, a0, a1
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; RV32-NEXT: srli a2, a2, 1
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; RV32-NEXT: add a1, a2, a1
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; RV32-NEXT: srli a1, a1, 2
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; RV32-NEXT: slli a2, a1, 3
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_7:
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; RV64: # %bb.0:
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; RV64-NEXT: li a2, -1
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; RV64-NEXT: slli a3, a1, 4
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; RV64-NEXT: srli a4, a0, 60
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; RV64-NEXT: or a3, a4, a3
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; RV64-NEXT: lui a4, %hi(.LCPI2_0)
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; RV64-NEXT: srli a2, a2, 4
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; RV64-NEXT: ld a4, %lo(.LCPI2_0)(a4)
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; RV64-NEXT: and a0, a0, a2
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; RV64-NEXT: and a2, a3, a2
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; RV64-NEXT: add a0, a0, a2
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; RV64-NEXT: srli a1, a1, 56
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: mulhu a1, a0, a4
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; RV64-NEXT: srli a1, a1, 1
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; RV64-NEXT: slli a2, a1, 3
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 7
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_9(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_9:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a2, 262144
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; RV32-NEXT: slli a3, a1, 2
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; RV32-NEXT: srli a4, a0, 30
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; RV32-NEXT: srli a1, a1, 28
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; RV32-NEXT: or a3, a4, a3
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; RV32-NEXT: lui a4, 233017
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; RV32-NEXT: addi a2, a2, -1
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; RV32-NEXT: and a0, a0, a2
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; RV32-NEXT: and a2, a3, a2
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; RV32-NEXT: add a0, a0, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: addi a1, a4, -455
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a1, a1, 1
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; RV32-NEXT: slli a2, a1, 3
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; RV32-NEXT: add a1, a2, a1
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_9:
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; RV64: # %bb.0:
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; RV64-NEXT: li a2, -1
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; RV64-NEXT: slli a3, a1, 4
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; RV64-NEXT: srli a4, a0, 60
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; RV64-NEXT: or a3, a4, a3
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; RV64-NEXT: lui a4, %hi(.LCPI3_0)
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; RV64-NEXT: srli a2, a2, 4
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; RV64-NEXT: ld a4, %lo(.LCPI3_0)(a4)
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; RV64-NEXT: and a0, a0, a2
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; RV64-NEXT: and a2, a3, a2
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; RV64-NEXT: add a0, a0, a2
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; RV64-NEXT: srli a1, a1, 56
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: mulhu a1, a0, a4
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; RV64-NEXT: slli a2, a1, 3
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 9
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_15(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_15:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 559241
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: addi a1, a2, -1911
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a1, a1, 3
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; RV32-NEXT: slli a2, a1, 4
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_15:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 559241
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, -1911
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: srli a1, a1, 3
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; RV64-NEXT: slli a2, a1, 4
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 15
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_17(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_17:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 986895
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: addi a2, a2, 241
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: mulhu a1, a0, a2
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; RV32-NEXT: srli a2, a1, 4
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; RV32-NEXT: andi a1, a1, -16
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_17:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 986895
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, 241
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: srli a2, a1, 4
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; RV64-NEXT: andi a1, a1, -16
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 17
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_255(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_255:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 526344
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: addi a1, a2, 129
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a1, a1, 7
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; RV32-NEXT: slli a2, a1, 8
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_255:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 526344
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, 129
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: srli a1, a1, 7
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; RV64-NEXT: slli a2, a1, 8
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 255
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_257(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_257:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 1044496
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: addi a2, a2, -255
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: mulhu a1, a0, a2
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; RV32-NEXT: srli a2, a1, 8
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; RV32-NEXT: andi a1, a1, -256
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_257:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 1044496
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, -255
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: srli a2, a1, 8
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; RV64-NEXT: andi a1, a1, -256
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 257
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_65535(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_65535:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: lui a2, 524296
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: addi a2, a2, 1
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; RV32-NEXT: mulhu a1, a0, a2
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; RV32-NEXT: srli a1, a1, 15
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; RV32-NEXT: slli a2, a1, 16
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_65535:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: lui a2, 524296
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: addi a2, a2, 1
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: slli a1, a2, 32
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; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: mulhu a1, a0, a1
|
|
; RV64-NEXT: srli a1, a1, 15
|
|
; RV64-NEXT: slli a2, a1, 16
|
|
; RV64-NEXT: sub a1, a1, a2
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: li a1, 0
|
|
; RV64-NEXT: ret
|
|
%a = urem iXLen2 %x, 65535
|
|
ret iXLen2 %a
|
|
}
|
|
|
|
define iXLen2 @test_urem_65537(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_65537:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: add a1, a0, a1
|
|
; RV32-NEXT: lui a2, 1048560
|
|
; RV32-NEXT: sltu a0, a1, a0
|
|
; RV32-NEXT: add a0, a1, a0
|
|
; RV32-NEXT: addi a1, a2, 1
|
|
; RV32-NEXT: mulhu a1, a0, a1
|
|
; RV32-NEXT: and a2, a1, a2
|
|
; RV32-NEXT: srli a1, a1, 16
|
|
; RV32-NEXT: or a1, a2, a1
|
|
; RV32-NEXT: sub a0, a0, a1
|
|
; RV32-NEXT: li a1, 0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_65537:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: add a1, a0, a1
|
|
; RV64-NEXT: lui a2, 1048560
|
|
; RV64-NEXT: sltu a0, a1, a0
|
|
; RV64-NEXT: addi a3, a2, 1
|
|
; RV64-NEXT: add a0, a1, a0
|
|
; RV64-NEXT: slli a1, a3, 32
|
|
; RV64-NEXT: add a1, a3, a1
|
|
; RV64-NEXT: mulhu a1, a0, a1
|
|
; RV64-NEXT: and a2, a1, a2
|
|
; RV64-NEXT: srli a1, a1, 16
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: sub a0, a0, a1
|
|
; RV64-NEXT: li a1, 0
|
|
; RV64-NEXT: ret
|
|
%a = urem iXLen2 %x, 65537
|
|
ret iXLen2 %a
|
|
}
|
|
|
|
define iXLen2 @test_urem_12(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_12:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: slli a2, a1, 30
|
|
; RV32-NEXT: srli a3, a0, 2
|
|
; RV32-NEXT: srli a1, a1, 2
|
|
; RV32-NEXT: or a2, a3, a2
|
|
; RV32-NEXT: lui a3, 699051
|
|
; RV32-NEXT: addi a3, a3, -1365
|
|
; RV32-NEXT: add a1, a2, a1
|
|
; RV32-NEXT: sltu a2, a1, a2
|
|
; RV32-NEXT: add a1, a1, a2
|
|
; RV32-NEXT: mulhu a2, a1, a3
|
|
; RV32-NEXT: srli a3, a2, 1
|
|
; RV32-NEXT: andi a2, a2, -2
|
|
; RV32-NEXT: add a2, a2, a3
|
|
; RV32-NEXT: sub a1, a1, a2
|
|
; RV32-NEXT: slli a1, a1, 2
|
|
; RV32-NEXT: andi a0, a0, 3
|
|
; RV32-NEXT: or a0, a1, a0
|
|
; RV32-NEXT: li a1, 0
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_12:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: slli a2, a1, 62
|
|
; RV64-NEXT: srli a3, a0, 2
|
|
; RV64-NEXT: lui a4, 699051
|
|
; RV64-NEXT: or a2, a3, a2
|
|
; RV64-NEXT: addi a3, a4, -1365
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: srli a1, a1, 2
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: sltu a2, a1, a2
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: mulhu a2, a1, a3
|
|
; RV64-NEXT: srli a3, a2, 1
|
|
; RV64-NEXT: andi a2, a2, -2
|
|
; RV64-NEXT: add a2, a2, a3
|
|
; RV64-NEXT: sub a1, a1, a2
|
|
; RV64-NEXT: slli a1, a1, 2
|
|
; RV64-NEXT: andi a0, a0, 3
|
|
; RV64-NEXT: or a0, a1, a0
|
|
; RV64-NEXT: li a1, 0
|
|
; RV64-NEXT: ret
|
|
%a = urem iXLen2 %x, 12
|
|
ret iXLen2 %a
|
|
}
|
|
|
|
; Divisor: 7 * 2^30 (has 30 trailing zeros, < HBitWidth for RV32 and RV64)
|
|
define iXLen2 @test_urem_7_shl_30(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_7_shl_30:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: slli a2, a1, 2
|
|
; RV32-NEXT: srli a3, a0, 30
|
|
; RV32-NEXT: lui a4, 262144
|
|
; RV32-NEXT: srli a1, a1, 28
|
|
; RV32-NEXT: or a2, a3, a2
|
|
; RV32-NEXT: lui a3, 599186
|
|
; RV32-NEXT: addi a4, a4, -1
|
|
; RV32-NEXT: addi a3, a3, 1171
|
|
; RV32-NEXT: and a2, a2, a4
|
|
; RV32-NEXT: and a0, a0, a4
|
|
; RV32-NEXT: add a1, a2, a1
|
|
; RV32-NEXT: mulhu a2, a1, a3
|
|
; RV32-NEXT: srli a2, a2, 2
|
|
; RV32-NEXT: slli a3, a2, 3
|
|
; RV32-NEXT: sub a2, a2, a3
|
|
; RV32-NEXT: add a1, a1, a2
|
|
; RV32-NEXT: slli a2, a1, 30
|
|
; RV32-NEXT: or a0, a2, a0
|
|
; RV32-NEXT: srli a1, a1, 2
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_7_shl_30:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: slli a2, a1, 34
|
|
; RV64-NEXT: srli a3, a0, 30
|
|
; RV64-NEXT: srli a1, a1, 26
|
|
; RV64-NEXT: or a2, a3, a2
|
|
; RV64-NEXT: lui a3, %hi(.LCPI11_0)
|
|
; RV64-NEXT: slli a0, a0, 34
|
|
; RV64-NEXT: ld a3, %lo(.LCPI11_0)(a3)
|
|
; RV64-NEXT: slli a2, a2, 4
|
|
; RV64-NEXT: srli a2, a2, 4
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: mulhu a2, a1, a3
|
|
; RV64-NEXT: slli a3, a2, 3
|
|
; RV64-NEXT: sub a2, a2, a3
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: slli a1, a1, 30
|
|
; RV64-NEXT: srli a0, a0, 34
|
|
; RV64-NEXT: or a0, a1, a0
|
|
; RV64-NEXT: li a1, 0
|
|
; RV64-NEXT: ret
|
|
%a = urem iXLen2 %x, u0x1C0000000
|
|
ret iXLen2 %a
|
|
}
|
|
|
|
; Divisor: 3 * 2^32 (has 32 trailing zeros, exactly HBitWidth for RV32)
|
|
define iXLen2 @test_urem_3_shl_32(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_3_shl_32:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: lui a2, 699051
|
|
; RV32-NEXT: addi a2, a2, -1365
|
|
; RV32-NEXT: mulhu a2, a1, a2
|
|
; RV32-NEXT: srli a3, a2, 1
|
|
; RV32-NEXT: andi a2, a2, -2
|
|
; RV32-NEXT: add a2, a2, a3
|
|
; RV32-NEXT: sub a1, a1, a2
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_3_shl_32:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: slli a2, a1, 32
|
|
; RV64-NEXT: srli a3, a0, 32
|
|
; RV64-NEXT: lui a4, 699051
|
|
; RV64-NEXT: or a2, a3, a2
|
|
; RV64-NEXT: addi a3, a4, -1365
|
|
; RV64-NEXT: slli a4, a3, 32
|
|
; RV64-NEXT: add a3, a3, a4
|
|
; RV64-NEXT: srli a1, a1, 32
|
|
; RV64-NEXT: slli a0, a0, 32
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: sltu a2, a1, a2
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: mulhu a2, a1, a3
|
|
; RV64-NEXT: srli a3, a2, 1
|
|
; RV64-NEXT: andi a2, a2, -2
|
|
; RV64-NEXT: add a2, a2, a3
|
|
; RV64-NEXT: sub a1, a1, a2
|
|
; RV64-NEXT: slli a1, a1, 32
|
|
; RV64-NEXT: srli a0, a0, 32
|
|
; RV64-NEXT: or a0, a1, a0
|
|
; RV64-NEXT: li a1, 0
|
|
; RV64-NEXT: ret
|
|
%a = urem iXLen2 %x, u0x300000000
|
|
ret iXLen2 %a
|
|
}
|
|
|
|
; Divisor: 7 * 2^60 (has 60 trailing zeros, > HBitWidth for RV32)
|
|
define iXLen2 @test_urem_7_shl_60(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_7_shl_60:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: srli a2, a1, 28
|
|
; RV32-NEXT: lui a3, 149797
|
|
; RV32-NEXT: slli a1, a1, 4
|
|
; RV32-NEXT: addi a3, a3, -1755
|
|
; RV32-NEXT: mulhu a3, a2, a3
|
|
; RV32-NEXT: slli a4, a3, 3
|
|
; RV32-NEXT: add a2, a2, a3
|
|
; RV32-NEXT: sub a2, a2, a4
|
|
; RV32-NEXT: slli a2, a2, 28
|
|
; RV32-NEXT: srli a1, a1, 4
|
|
; RV32-NEXT: or a1, a2, a1
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_7_shl_60:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: slli a2, a1, 4
|
|
; RV64-NEXT: srli a3, a0, 60
|
|
; RV64-NEXT: li a4, -1
|
|
; RV64-NEXT: srli a1, a1, 56
|
|
; RV64-NEXT: or a2, a3, a2
|
|
; RV64-NEXT: lui a3, %hi(.LCPI13_0)
|
|
; RV64-NEXT: ld a3, %lo(.LCPI13_0)(a3)
|
|
; RV64-NEXT: srli a4, a4, 4
|
|
; RV64-NEXT: and a2, a2, a4
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: mulhu a2, a1, a3
|
|
; RV64-NEXT: slli a3, a2, 3
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: sub a1, a1, a3
|
|
; RV64-NEXT: slli a1, a1, 60
|
|
; RV64-NEXT: and a0, a0, a4
|
|
; RV64-NEXT: or a0, a1, a0
|
|
; RV64-NEXT: li a1, 0
|
|
; RV64-NEXT: ret
|
|
%a = urem iXLen2 %x, u0x7000000000000000
|
|
ret iXLen2 %a
|
|
}
|
|
|
|
; Divisor: 37 * 2^XLen (has XLen trailing zeros)
|
|
define iXLen2 @test_urem_37_shl_XL(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_37_shl_XL:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: srli a2, a1, 18
|
|
; RV32-NEXT: slli a1, a1, 14
|
|
; RV32-NEXT: lui a3, 64
|
|
; RV32-NEXT: srli a1, a1, 14
|
|
; RV32-NEXT: sub a1, a1, a2
|
|
; RV32-NEXT: lui a2, 765177
|
|
; RV32-NEXT: addi a3, a3, 1
|
|
; RV32-NEXT: addi a2, a2, 333
|
|
; RV32-NEXT: add a1, a1, a3
|
|
; RV32-NEXT: mulhu a2, a1, a2
|
|
; RV32-NEXT: sub a3, a1, a2
|
|
; RV32-NEXT: srli a3, a3, 1
|
|
; RV32-NEXT: add a2, a3, a2
|
|
; RV32-NEXT: srli a2, a2, 5
|
|
; RV32-NEXT: li a3, 37
|
|
; RV32-NEXT: mul a2, a2, a3
|
|
; RV32-NEXT: sub a1, a1, a2
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_37_shl_XL:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: srli a2, a1, 36
|
|
; RV64-NEXT: lui a3, %hi(.LCPI14_0)
|
|
; RV64-NEXT: ld a3, %lo(.LCPI14_0)(a3)
|
|
; RV64-NEXT: slli a1, a1, 28
|
|
; RV64-NEXT: srli a1, a1, 28
|
|
; RV64-NEXT: add a1, a1, a2
|
|
; RV64-NEXT: mulhu a2, a1, a3
|
|
; RV64-NEXT: li a3, 37
|
|
; RV64-NEXT: mul a2, a2, a3
|
|
; RV64-NEXT: sub a1, a1, a2
|
|
; RV64-NEXT: ret
|
|
%a = shl iXLen2 37, XLen
|
|
%b = urem iXLen2 %x, %a
|
|
ret iXLen2 %b
|
|
}
|
|
|
|
; Divisor: 3 * 2^(XLen+5) (has XLen+ trailing zeros)
|
|
define iXLen2 @test_urem_3_shl_XLplus5(iXLen2 %x) nounwind {
|
|
; RV32-LABEL: test_urem_3_shl_XLplus5:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: srli a2, a1, 5
|
|
; RV32-NEXT: lui a3, 349525
|
|
; RV32-NEXT: addi a3, a3, 1366
|
|
; RV32-NEXT: mulhu a3, a2, a3
|
|
; RV32-NEXT: slli a4, a3, 1
|
|
; RV32-NEXT: sub a2, a2, a3
|
|
; RV32-NEXT: sub a2, a2, a4
|
|
; RV32-NEXT: slli a2, a2, 5
|
|
; RV32-NEXT: andi a1, a1, 31
|
|
; RV32-NEXT: or a1, a2, a1
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: test_urem_3_shl_XLplus5:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: lui a2, %hi(.LCPI15_0)
|
|
; RV64-NEXT: ld a2, %lo(.LCPI15_0)(a2)
|
|
; RV64-NEXT: srli a3, a1, 5
|
|
; RV64-NEXT: mulhu a2, a3, a2
|
|
; RV64-NEXT: slli a4, a2, 1
|
|
; RV64-NEXT: sub a3, a3, a2
|
|
; RV64-NEXT: sub a3, a3, a4
|
|
; RV64-NEXT: slli a3, a3, 5
|
|
; RV64-NEXT: andi a1, a1, 31
|
|
; RV64-NEXT: or a1, a3, a1
|
|
; RV64-NEXT: ret
|
|
%a = shl iXLen2 96, XLen
|
|
%b = urem iXLen2 %x, %a
|
|
ret iXLen2 %b
|
|
}
|