TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/sra-xor-sra.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s

; Test folding of: (sra (xor (sra x, c1), -1), c2) -> (sra (xor x, -1), c3)
; Original motivating example: should merge sra+sra across xor
define i16 @not_invert_signbit_splat_mask(i8 %x, i16 %y) {
; CHECK-LABEL: not_invert_signbit_splat_mask:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a0, a0, 56
; CHECK-NEXT:    srai a0, a0, 62
; CHECK-NEXT:    not a0, a0
; CHECK-NEXT:    and a0, a0, a1
; CHECK-NEXT:    ret
  %a = ashr i8 %x, 6
  %n = xor i8 %a, -1
  %s = sext i8 %n to i16
  %r = and i16 %s, %y
  ret i16 %r
}

; Edge case
define i16 @sra_xor_sra_overflow(i8 %x, i16 %y) {
; CHECK-LABEL: sra_xor_sra_overflow:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 0
; CHECK-NEXT:    ret
  %a = ashr i8 %x, 10
  %n = xor i8 %a, -1
  %s = sext i8 %n to i16
  %r = and i16 %s, %y
  ret i16 %r
}