derek.holloway
7502bf64a4
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728 lines
21 KiB
LLVM
728 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IM
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; RUN: llc -mtriple=riscv32 -mattr=+m,+xqciac -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IMXQCIAC
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; RUN: llc -mtriple=riscv32 -mattr=+m,+xqciac,+zba -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IZBAMXQCIAC
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define dso_local i32 @mul(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: mul:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a0, a1, 5
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: mul:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: li a0, 33
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; RV32IMXQCIAC-NEXT: mul a0, a1, a0
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: mul:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: li a0, 33
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; RV32IZBAMXQCIAC-NEXT: mul a0, a1, a0
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 33
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ret i32 %mul
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}
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define dso_local i32 @muliadd(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, 165
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 165
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 165
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 165
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @muliadd2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, 1111
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 1111
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 1111
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 1111
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @muliadd_neg(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd_neg:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, -165
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd_neg:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, -165
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd_neg:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, -165
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, -165
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @muliadd_neg2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd_neg2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, -2045
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd_neg2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, -2045
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd_neg2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, -2045
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, -2045
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2immplus1(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2immplus1:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a2, a1, 5
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: add a0, a2, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2immplus1:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 33
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2immplus1:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 33
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 33
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2immminus2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2immminus2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a2, a1, 1
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; RV32IM-NEXT: slli a1, a1, 7
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; RV32IM-NEXT: sub a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2immminus2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 126
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2immminus2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 126
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 126
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2minuspow2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2minuspow2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a2, a1, 7
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; RV32IM-NEXT: slli a1, a1, 8
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2minuspow2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 384
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2minuspow2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 384
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 384
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @gtsimm12(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: gtsimm12:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: lui a2, 1
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; RV32IM-NEXT: addi a2, a2, 477
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: gtsimm12:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: lui a2, 1
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; RV32IMXQCIAC-NEXT: addi a2, a2, 477
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; RV32IMXQCIAC-NEXT: mul a1, a1, a2
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; RV32IMXQCIAC-NEXT: add a0, a0, a1
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: gtsimm12:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: lui a2, 1
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; RV32IZBAMXQCIAC-NEXT: addi a2, a2, 477
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; RV32IZBAMXQCIAC-NEXT: mul a1, a1, a2
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; RV32IZBAMXQCIAC-NEXT: add a0, a0, a1
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 4573
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a1, a1, 5
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 32
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @shxadd(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: shxadd:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a1, a1, 1
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: shxadd:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: slli a1, a1, 1
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; RV32IMXQCIAC-NEXT: add a0, a0, a1
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: shxadd:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.c.muliadd a0, a1, 2
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 2
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @shladd(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: shladd:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a1, a1, 31
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: shladd:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: shladd:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%shl = shl nsw i32 %b, 31
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%add = add nsw i32 %shl, %a
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ret i32 %add
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}
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define dso_local i64 @shladd64(i64 %a, i64 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: shladd64:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: srli a4, a2, 1
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; RV32IM-NEXT: slli a3, a3, 31
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; RV32IM-NEXT: slli a2, a2, 31
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; RV32IM-NEXT: or a3, a3, a4
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; RV32IM-NEXT: add a0, a2, a0
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; RV32IM-NEXT: sltu a2, a0, a2
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; RV32IM-NEXT: add a1, a3, a1
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; RV32IM-NEXT: add a1, a1, a2
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: shladd64:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: srli a4, a2, 1
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; RV32IMXQCIAC-NEXT: qc.shladd a0, a2, a0, 31
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; RV32IMXQCIAC-NEXT: slli a2, a2, 31
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; RV32IMXQCIAC-NEXT: qc.shladd a3, a3, a4, 31
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; RV32IMXQCIAC-NEXT: sltu a2, a0, a2
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; RV32IMXQCIAC-NEXT: add a1, a1, a3
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; RV32IMXQCIAC-NEXT: add a1, a1, a2
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: shladd64:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: srli a4, a2, 1
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; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a2, a0, 31
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; RV32IZBAMXQCIAC-NEXT: slli a2, a2, 31
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; RV32IZBAMXQCIAC-NEXT: qc.shladd a3, a3, a4, 31
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; RV32IZBAMXQCIAC-NEXT: sltu a2, a0, a2
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; RV32IZBAMXQCIAC-NEXT: add a1, a1, a3
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; RV32IZBAMXQCIAC-NEXT: add a1, a1, a2
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%shl = shl nsw i64 %b, 31
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%add = add nsw i64 %shl, %a
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ret i64 %add
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}
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define dso_local i32 @shladd_ordisjoint(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: shladd_ordisjoint:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a1, a1, 22
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; RV32IM-NEXT: or a0, a1, a0
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: shladd_ordisjoint:
|
|
; RV32IMXQCIAC: # %bb.0: # %entry
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 22
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: shladd_ordisjoint:
|
|
; RV32IZBAMXQCIAC: # %bb.0: # %entry
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 22
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
entry:
|
|
%shl = shl nsw i32 %b, 22
|
|
%or = or disjoint i32 %shl, %a
|
|
ret i32 %or
|
|
}
|
|
|
|
define dso_local i32 @shladdc1c2(i32 %a, i32 %b) local_unnamed_addr #0 {
|
|
; RV32IM-LABEL: shladdc1c2:
|
|
; RV32IM: # %bb.0: # %entry
|
|
; RV32IM-NEXT: slli a0, a0, 31
|
|
; RV32IM-NEXT: slli a1, a1, 26
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: shladdc1c2:
|
|
; RV32IMXQCIAC: # %bb.0: # %entry
|
|
; RV32IMXQCIAC-NEXT: slli a1, a1, 26
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: shladdc1c2:
|
|
; RV32IZBAMXQCIAC: # %bb.0: # %entry
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5
|
|
; RV32IZBAMXQCIAC-NEXT: slli a0, a0, 26
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
entry:
|
|
%shlc1 = shl nsw i32 %a, 31
|
|
%shlc2 = shl nsw i32 %b, 26
|
|
%add = add nsw i32 %shlc1, %shlc2
|
|
ret i32 %add
|
|
}
|
|
|
|
define dso_local i32 @shxaddc1c2(i32 %a, i32 %b) local_unnamed_addr #0 {
|
|
; RV32IM-LABEL: shxaddc1c2:
|
|
; RV32IM: # %bb.0: # %entry
|
|
; RV32IM-NEXT: slli a0, a0, 31
|
|
; RV32IM-NEXT: slli a1, a1, 28
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: shxaddc1c2:
|
|
; RV32IMXQCIAC: # %bb.0: # %entry
|
|
; RV32IMXQCIAC-NEXT: slli a1, a1, 28
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: shxaddc1c2:
|
|
; RV32IZBAMXQCIAC: # %bb.0: # %entry
|
|
; RV32IZBAMXQCIAC-NEXT: sh3add a0, a0, a1
|
|
; RV32IZBAMXQCIAC-NEXT: slli a0, a0, 28
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
entry:
|
|
%shlc1 = shl nsw i32 %a, 31
|
|
%shlc2 = shl nsw i32 %b, 28
|
|
%add = add nsw i32 %shlc1, %shlc2
|
|
ret i32 %add
|
|
}
|
|
|
|
define dso_local i64 @shladdc1c264(i64 %a, i64 %b) local_unnamed_addr #0 {
|
|
; RV32IM-LABEL: shladdc1c264:
|
|
; RV32IM: # %bb.0: # %entry
|
|
; RV32IM-NEXT: slli a1, a0, 23
|
|
; RV32IM-NEXT: srli a0, a2, 12
|
|
; RV32IM-NEXT: slli a3, a3, 20
|
|
; RV32IM-NEXT: or a3, a3, a0
|
|
; RV32IM-NEXT: slli a0, a2, 20
|
|
; RV32IM-NEXT: add a1, a1, a3
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: shladdc1c264:
|
|
; RV32IMXQCIAC: # %bb.0: # %entry
|
|
; RV32IMXQCIAC-NEXT: srli a1, a2, 12
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a1, a3, a1, 20
|
|
; RV32IMXQCIAC-NEXT: slli a2, a2, 20
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a1, a0, a1, 23
|
|
; RV32IMXQCIAC-NEXT: mv a0, a2
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: shladdc1c264:
|
|
; RV32IZBAMXQCIAC: # %bb.0: # %entry
|
|
; RV32IZBAMXQCIAC-NEXT: srli a1, a2, 12
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a3, a1, 20
|
|
; RV32IZBAMXQCIAC-NEXT: slli a2, a2, 20
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a0, a1, 23
|
|
; RV32IZBAMXQCIAC-NEXT: mv a0, a2
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
entry:
|
|
%shlc1 = shl nsw i64 %a, 55
|
|
%shlc2 = shl nsw i64 %b, 20
|
|
%add = add nsw i64 %shlc1, %shlc2
|
|
ret i64 %add
|
|
}
|
|
|
|
define dso_local i32 @shladdc1equalc2(i32 %a, i32 %b) local_unnamed_addr #0 {
|
|
; RV32IM-LABEL: shladdc1equalc2:
|
|
; RV32IM: # %bb.0: # %entry
|
|
; RV32IM-NEXT: slli a0, a0, 12
|
|
; RV32IM-NEXT: slli a1, a1, 12
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: shladdc1equalc2:
|
|
; RV32IMXQCIAC: # %bb.0: # %entry
|
|
; RV32IMXQCIAC-NEXT: slli a1, a1, 12
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 12
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: shladdc1equalc2:
|
|
; RV32IZBAMXQCIAC: # %bb.0: # %entry
|
|
; RV32IZBAMXQCIAC-NEXT: slli a1, a1, 12
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 12
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
entry:
|
|
%shlc1 = shl nsw i32 %a, 12
|
|
%shlc2 = shl nsw i32 %b, 12
|
|
%add = add nsw i32 %shlc1, %shlc2
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @testmuliaddnegimm(i32 %a) {
|
|
; RV32IM-LABEL: testmuliaddnegimm:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a1, a0, 1
|
|
; RV32IM-NEXT: add a0, a1, a0
|
|
; RV32IM-NEXT: li a1, 3
|
|
; RV32IM-NEXT: sub a0, a1, a0
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: testmuliaddnegimm:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: li a1, 3
|
|
; RV32IMXQCIAC-NEXT: qc.muliadd a1, a0, -3
|
|
; RV32IMXQCIAC-NEXT: mv a0, a1
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: li a1, 3
|
|
; RV32IZBAMXQCIAC-NEXT: qc.muliadd a1, a0, -3
|
|
; RV32IZBAMXQCIAC-NEXT: mv a0, a1
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%mul = mul i32 %a, -3
|
|
%add = add i32 %mul, 3
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @add_shl_OneUse_1(i32 %x) {
|
|
; RV32IM-LABEL: add_shl_OneUse_1:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: ori a1, a0, 1
|
|
; RV32IM-NEXT: slli a0, a0, 4
|
|
; RV32IM-NEXT: ori a0, a0, 16
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: add_shl_OneUse_1:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: ori a0, a0, 1
|
|
; RV32IMXQCIAC-NEXT: qc.c.muliadd a0, a0, 16
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: add_shl_OneUse_1:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: ori a0, a0, 1
|
|
; RV32IZBAMXQCIAC-NEXT: qc.c.muliadd a0, a0, 16
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%or = or i32 %x, 1
|
|
%mul = shl i32 %or, 4
|
|
%add = add i32 %mul, %or
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @add_shl_OneUse_2(i32 %x) {
|
|
; RV32IM-LABEL: add_shl_OneUse_2:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: ori a1, a0, 1
|
|
; RV32IM-NEXT: slli a0, a0, 10
|
|
; RV32IM-NEXT: ori a0, a0, 1024
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: add_shl_OneUse_2:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: ori a0, a0, 1
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a0, 10
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: add_shl_OneUse_2:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: ori a0, a0, 1
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a0, 10
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%or = or i32 %x, 1
|
|
%mul = shl i32 %or, 10
|
|
%add = add i32 %mul, %or
|
|
ret i32 %add
|
|
}
|
|
|
|
; For shifts greater than 10 the ori immediate cannot fit within 12 bits so
|
|
; we don't commute with shift and generate qc.shaldd
|
|
define i32 @add_shl_OneUse_3(i32 %x) {
|
|
; RV32IM-LABEL: add_shl_OneUse_3:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: ori a0, a0, 1
|
|
; RV32IM-NEXT: slli a1, a0, 11
|
|
; RV32IM-NEXT: add a0, a1, a0
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: add_shl_OneUse_3:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: ori a0, a0, 1
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a0, 11
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: add_shl_OneUse_3:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: ori a0, a0, 1
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a0, 11
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%or = or i32 %x, 1
|
|
%mul = shl i32 %or, 11
|
|
%add = add i32 %mul, %or
|
|
ret i32 %add
|
|
}
|
|
|
|
; The shift left gets converted early and as a result we cannot
|
|
; generate the qc.shladd.
|
|
; FIXME: Should we handle this case and generate qc.shladd if possible?
|
|
define i32 @add_shl_moreOneUse_4(i32 %x) {
|
|
; RV32IM-LABEL: add_shl_moreOneUse_4:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: ori a0, a0, 7
|
|
; RV32IM-NEXT: lui a1, 524288
|
|
; RV32IM-NEXT: add a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: add_shl_moreOneUse_4:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: ori a0, a0, 7
|
|
; RV32IMXQCIAC-NEXT: lui a1, 524288
|
|
; RV32IMXQCIAC-NEXT: add a0, a0, a1
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: add_shl_moreOneUse_4:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: ori a0, a0, 7
|
|
; RV32IZBAMXQCIAC-NEXT: lui a1, 524288
|
|
; RV32IZBAMXQCIAC-NEXT: add a0, a0, a1
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%or = or i32 %x, 7
|
|
%mul = shl i32 %or, 31
|
|
%add = add i32 %mul, %or
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @select20(i1 zeroext %x) {
|
|
; RV32IM-LABEL: select20:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: neg a0, a0
|
|
; RV32IM-NEXT: andi a0, a0, 20
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: select20:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: qc.c.muliadd a0, a0, 19
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: select20:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: qc.c.muliadd a0, a0, 19
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%select = select i1 %x, i32 20, i32 0
|
|
ret i32 %select
|
|
}
|
|
|
|
define i32 @select65(i1 zeroext %x) {
|
|
; RV32IM-LABEL: select65:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: neg a0, a0
|
|
; RV32IM-NEXT: andi a0, a0, 65
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: select65:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: qc.muliadd a0, a0, 64
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: select65:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a0, 64
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%select = select i1 %x, i32 65, i32 0
|
|
ret i32 %select
|
|
}
|
|
|
|
|
|
define i32 @select1111(i1 zeroext %x) {
|
|
; RV32IM-LABEL: select1111:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: neg a0, a0
|
|
; RV32IM-NEXT: andi a0, a0, 1111
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: select1111:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: qc.muliadd a0, a0, 1110
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: select1111:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a0, 1110
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%select = select i1 %x, i32 1111, i32 0
|
|
ret i32 %select
|
|
}
|
|
|
|
define i32 @select8193(i1 zeroext %x) {
|
|
; RV32IM-LABEL: select8193:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: neg a0, a0
|
|
; RV32IM-NEXT: lui a1, 2
|
|
; RV32IM-NEXT: addi a1, a1, 1
|
|
; RV32IM-NEXT: and a0, a0, a1
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: select8193:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a0, 13
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: select8193:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a0, 13
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%select = select i1 %x, i32 8193, i32 0
|
|
ret i32 %select
|
|
}
|
|
|
|
|
|
define i64 @select_int64_min(i1 zeroext %x) {
|
|
; RV32IM-LABEL: select_int64_min:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: slli a1, a0, 31
|
|
; RV32IM-NEXT: li a0, 0
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: select_int64_min:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: slli a1, a0, 31
|
|
; RV32IMXQCIAC-NEXT: li a0, 0
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: select_int64_min:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: slli a1, a0, 31
|
|
; RV32IZBAMXQCIAC-NEXT: li a0, 0
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%select = select i1 %x, i64 -9223372036854775808, i64 0
|
|
ret i64 %select
|
|
}
|
|
|
|
define i32 @neg_coefficient(i1 zeroext %x) nounwind {
|
|
; RV32IM-LABEL: neg_coefficient:
|
|
; RV32IM: # %bb.0:
|
|
; RV32IM-NEXT: neg a0, a0
|
|
; RV32IM-NEXT: andi a0, a0, -32
|
|
; RV32IM-NEXT: ret
|
|
;
|
|
; RV32IMXQCIAC-LABEL: neg_coefficient:
|
|
; RV32IMXQCIAC: # %bb.0:
|
|
; RV32IMXQCIAC-NEXT: qc.muliadd a0, a0, -33
|
|
; RV32IMXQCIAC-NEXT: ret
|
|
;
|
|
; RV32IZBAMXQCIAC-LABEL: neg_coefficient:
|
|
; RV32IZBAMXQCIAC: # %bb.0:
|
|
; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a0, -33
|
|
; RV32IZBAMXQCIAC-NEXT: ret
|
|
%cond = select i1 %x, i32 -32, i32 0
|
|
ret i32 %cond
|
|
}
|